Transaction-Level Platform Creation

Chapter
Part of the Embedded Systems book series (EMSY)

Abstract

 Chapter 5 looked at the creation of a system-level virtual prototype that was used primarily for software and system-level functional verification. It addressed many of the issues associated with adding major architectural elements, such as processors, buses, and memories. Many of the issues associated with HW/SW partitioning were also dealt within  Chapter 6 and  7. These chapters took a top-down approach to the problem. They started from the highest level of functional description and refined the models by adding information associated with the major architectural decisions. In this chapter we will introduce a flow in which the hardware is modeled incrementally and integrated into a system that may then be used for hardware verification, more detailed architectural exploration, and software integration. These platforms are created at the behavioral transaction level and often referred to as transaction-level platforms (TLPs).

Keywords

Product Line Stim Harness 

References

  1. 1.
  2. 2.
    Migrating to Transaction-Level Modeling in SystemC. Aldec/Doulos Webinar Jan 29th 2009Google Scholar
  3. 3.
    Bart Vanthournout. An Insider’s View on the Making of the New TLM-2.0 Standard. http://www.dac.com/newsletter/shownewsletter.aspx?newsid=34
  4. 4.
    Brian Bailey, Grant Martin, Thomas Anderson (Eds.). Taxonomies for the Development and Verification of Digital systems, Springer, 2005Google Scholar
  5. 5.
    Brian Bailey, Grant Martin, Andrew Piziali. ESL Design and Verification: A Prescription for Electronic System Level Methodology, Elsevier Morgan Kaufmann, 2007.Google Scholar
  6. 6.
    Mixed-Abstraction Virtual System Prototypes Close SOC Design Gaps. SoCentral. April 2006 http://www.soccentral.com/results.asp?EntryID=18709
  7. 7.
    Bill Murray. OSCI TLM-2 Proposal – The Debate Begins. SCDSource 1/9/2008. http://www.scdsource.com/article.php?id=84
  8. 8.
    Lukai Cai, Daniel Gajski. “Transaction level modeling: an overview,” in First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, Newport Beach, CA, 2003, pp. 19–24.Google Scholar
  9. 9.
    OCP Organization Website http://www.ocpip.org/home
  10. 10.
    Tim Kogel, Anssi Haverinen, James Aldis. OCP TLM for Architectural Modeling. http://www.ocpip.org/socket/whitepapers/OCP_TLM_for_Architectural_Modeling.pdf
  11. 11.
    Frank Ghenassia (Ed.). Transaction-Level Modeling with SystemC, Springer, 2005Google Scholar
  12. 12.
    Shashi Bhutada. A Scalable Approach for TLM Across SystemC and SystemVerilog. Mentor Graphics white Paper.Google Scholar
  13. 13.
    William W. LaRue, Sherry Solden, Bishnupriya Bhattacharya. Functional and Performance Modeling of Concurrency in VCC, Concurrency and Hardware Design, Springer, LNCS volume 2549, 191–227, 2002Google Scholar
  14. 14.
    Property Specification Language Reference Manual http://www.eda.org/vfv/docs/PSL -v1.1.pdf
  15. 15.
    SystemVerilog home page: http://www.systemverilog.org/
  16. 16.
    Bill Chown. System-level validation increases design productivity and saves errors. Mentor Graphics white paper.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.BeavertonUSA
  2. 2.Tensilica Inc.Santa ClaraUSA

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