Testbench Models

Part of the Embedded Systems book series (EMSY)


Verification has become as expensive and as important as design, and as such models and languages for verification are emerging that are highly directed toward their intended function. Most of what we think of as verification today is implementation verification taking place at the RTL level of abstraction or physical verification taking place at even lower levels of abstraction. Very little of the total verification effort goes into design verification. To put that another way, we spend most of our time verifying that we have implemented something correctly, rather than determining that we have specified the right thing, or that the collection of pieces that are being assembled are capable of performing the right function within the constraints imposed by the specification.


Coverage Model Functional Coverage Verification Task Verification Tool Code Coverage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.BeavertonUSA
  2. 2.Tensilica Inc.Santa ClaraUSA

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