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3D Physical Design

  • Jason Cong
  • Guojie Luo
Chapter

Abstract

The physical design process for 3D ICs is similar to that used for the traditional 2D physical design, in a sense that it transforms the circuit representation from a netlist into a geometric representation by the steps of floorplanning, placement, and ­routing. While the multiple-layer metals have already had 3D structure in ­traditional ICs for interconnects, the 3D IC technologies allow multiple layers of logical devices to be integrated in the third dimension by bonding stacks of multiple “tiers” to form 3D chips. Each tier, which is similar to a traditional 2D IC, consists of one silicon layer and several metal layers, and different tiers are connected by through-silicon vias (TS via).

Keywords

Silicon Layer Physical Design Placement Approach Global Placement Total Wirelength 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

This study is supported by the National Science Foundation (NSF) under CCF-0430077 and CCF-0528583.

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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.University of CaliforniaLos AngelesUSA

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