TSV-Based 3D Integration

  • James Burns


Theoretical studies in the 1980s [1, 2] suggested that significant reductions in signal delay and power consumption could be achieved with 3D integrated circuits (3D ICs). A 3D IC is a chip that consists of multiple tiers of thinned-active 2D integrated circuits (2D ICs) that are stacked, bonded, and electrically connected with vertical vias formed through silicon or oxide layers and whose placement within the tiers is discretionary. The term “tier” is used to distinguish the transferred layers of a 3D IC from design and physical layers and is the functional section of a chip or wafer that consists of the active silicon, the interconnect, and, for a silicon-on-oxide (SOI) wafer, the buried oxide (BOX). The basic features of a 3D IC are illustrated in Fig. 2.1 in a symbolic drawing along with a cross-section of an actual 3D IC. The TSV (through silicon via) is an essential feature of the 3D IC technology and is the vertical-electrical connection formed between tiers and through silicon or oxide. A TSV is formed by aligning, defining, and etching a cavity between two tiers to expose an electrode in the lower tier; lining the sidewalls of the cavity with an insulator; and filling the cavity with metal or doped polysilicon to complete the connection. A TSV drawing and a cross-section of a TSV are shown in Fig. 2.2.


Multichip Module CMOS Readout Base Wafer Bond Void Symbolic Drawing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The work was sponsored by the Defense Advanced Research Projects Agency under Air Force contract #FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government.


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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Lincoln LaboratoryMassachusetts Institute of TechnologyLexingtonUSA

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