TSV-Based 3D Integration



Theoretical studies in the 1980s [1, 2] suggested that significant reductions in signal delay and power consumption could be achieved with 3D integrated circuits (3D ICs). A 3D IC is a chip that consists of multiple tiers of thinned-active 2D integrated circuits (2D ICs) that are stacked, bonded, and electrically connected with vertical vias formed through silicon or oxide layers and whose placement within the tiers is discretionary. The term “tier” is used to distinguish the transferred layers of a 3D IC from design and physical layers and is the functional section of a chip or wafer that consists of the active silicon, the interconnect, and, for a silicon-on-oxide (SOI) wafer, the buried oxide (BOX). The basic features of a 3D IC are illustrated in Fig. 2.1 in a symbolic drawing along with a cross-section of an actual 3D IC. The TSV (through silicon via) is an essential feature of the 3D IC technology and is the vertical-electrical connection formed between tiers and through silicon or oxide. A TSV is formed by aligning, defining, and etching a cavity between two tiers to expose an electrode in the lower tier; lining the sidewalls of the cavity with an insulator; and filling the cavity with metal or doped polysilicon to complete the connection. A TSV drawing and a cross-section of a TSV are shown in Fig. 2.2.


Multichip Module CMOS Readout Base Wafer Bond Void Symbolic Drawing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The work was sponsored by the Defense Advanced Research Projects Agency under Air Force contract #FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government.


  1. 1.
    Reber M, Tielert R (1996) Benefits of vertically stacked integrated circuits for sequential logic. In: Proceedings of the IEEE international symposium on circuits and systems, vol 4, pp 121–124Google Scholar
  2. 2.
    Akasaka Y (1986) Three-dimensional IC trends. Proc IEEE 74(12):1703–1714CrossRefGoogle Scholar
  3. 3.
    Chan VWC, Chan PCH, Chan M (2000) Three dimensional CMOS integrated circuits on large grain polysilicon films. In: Technical digest - IEEE international electron devices meeting, pp. 161–164Google Scholar
  4. 4.
    Lea R, Jalowiecki I, Boughton D, Yamaguchi J, Pepe A, Ozguz V, Carson J (1999) A 3-D stacked chip packaging solution for miniaturized massively parallel processing. IEEE Trans Adv Packag 22(6):424–432CrossRefGoogle Scholar
  5. 5.
    Aull BF, Loomis AH, Gregory J, Young D (1998) Geiger-mode avalanche photodiode arrays integrated with CMOS timing circuits. In: IEEE annual device research conference digest, pp 58–59Google Scholar
  6. 6.
    Warner K, Burns J, Keast C, Kunz R, Lennon D, Loomis A, Mowers W, Yost D (2002) Low-temperature oxide-bonded three-dimensional integrated circuits. In: IEEE international SOI conference proceedings, pp 123–124Google Scholar
  7. 7.
    Burns J, McIlrath L, Hopwood J, Keast C, Vu DP, Warner K, Wyatt P (2000) An SOI-based three-dimensional integrated circuit technology. In: IEEE international SOI conference proceedings, pp 20–21Google Scholar
  8. 8.
    Topol A, Tulipe D, Shi S, Alam S, Frank D, Steen S, Vichiconti J, Posillico D, Cobb M, Medd S, Patel J, Goma S, DiMilia D, Farinelli M, Wang C, Conti R, Canaperi D, Deligianni L, Kumar A, Kwietniak T, D’Emic C, Ott J, Young A, Ieong M (2005) Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs). In Technical Digest - IEEE International Electron Devices Meeting, pp. 363–366Google Scholar
  9. 9.
    Reif R et al (2002) 3-D interconnects using Cu wafer bonding: technology and applications. In: Advanced metallization conference (AMC)Google Scholar
  10. 10.
    Warner K, Chen C, D’Onofrio R, Keast C, Poesse S (2004) An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication. In IEEE international SOI conference proceedings, pp 71–72Google Scholar
  11. 11.
    Fukushima T, Yamada Y, Kikuchi H, Koyanagi M (2005) New three-dimensional integration technology using self-assembly technique. In: Technical digest – IEEE international electron devices meeting, pp. 359–362Google Scholar
  12. 12.
    Tropol AW, La Tulipe DC Jr, Shi L, Frank DJ, Bernstein K, Sheen SE, Kumar A et al (2006) Three-dimensional integrated circuits. IBM J Res Dev 50(4/5):491–506CrossRefGoogle Scholar
  13. 13.
    Tezzaron Semiconductor, Naperville, IL 60563, http://www.tezzaron.com/technology/FaStack.htm
  14. 14.
    Burns JA, Aull BF, Chen CK, Chen C-L, Keast CL, Knecht JM, Suntharalingam V, Warner K, Wyatt PW, Yost D-RW (2006) A wafer-scale 3-D circuit integration technology. IEEE Trans Electron Devices 53(10):2507–2516CrossRefGoogle Scholar
  15. 15.
    Van Olmen J, Mercha A, Katti G, Huyghebaert C, Van Aelst J, Seppala E et al (), “3D stacked IC demonstration using a through silicon via first approach. IMEC. http://www.imec.be/ScientificReport/SR2008/HTML/1224951.html
  16. 16.
    (2008) International Technology Roadmap for Semiconductors: ITRS. Semiconductor Industry Association, San Jose, CA http://www.itrs.net/Links/2008ITRS/Home2008.htm
  17. 17.
    Knickerebocker JU, Andry PS, Dang B, Horton RR, Interrante MJ, Patel CS et al (2006) Three-dimensional silicon integration. IBM J Res Dev 50(4/5):553–567Google Scholar
  18. 18.
    Burns J, McIlrath L, Keast C, Lewis C, Loomis A, Warner K, Wyatt P (2001) Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip. In: Digest of technical papers. IEEE international solid-state circuits conference, pp 268–269, 453Google Scholar
  19. 19.
    Knecht J, Yost D, Burns J, Chen C, Keast C, Warner K (2005) 3D via etch development for 3D circuit integration in FDSOI. In IEEE Int. SOI Conf. Proc., pp 104–105Google Scholar
  20. 20.
    Maszara WP, Goetz G, Caviglia A, McKitterick JB (1988) Bonding of silicon wafers for silicon-on-insulator. J Appl Phys 64(10):4943–4950CrossRefGoogle Scholar
  21. 21.
    Chen CL, Chen CK, Burns JA, Yost D-R, Warner K, Knecht JM, Wyatt PW, Shibles DA, Keast CL (2007) Thermal effects of three dimensional integrated circuits stacks. In: IEEE international SOI conference proceedings, pp 91–92Google Scholar
  22. 22.
    Sri-Jayantha SM, McVicker G, Bernstein K, Knickerbocker JU (2006) Thermalmechanical modeling of 3D electronic packages. IBM J Res Dev 50(4/5):553–567, 623–634Google Scholar
  23. 23.
    Mentor Graphics, IC Nanometer Design Tool SuiteGoogle Scholar
  24. 24.
    Cadence Virtuoso Design ToolGoogle Scholar
  25. 25.
    Suntharalingam V, Berger R, Clark S, Knecht J, Messier A, Newcomb K, Rathman D, Slattery R, Soares A, Stevenson C, Warner K, Young D, Ang LP, Mansoorian B, Shaver D (2009) A four-side tileable, back illuminated, three-dimensionally integrated megapixel CMOS image sensor. In: Digest of technical papers. IEEE international solid-state circuits conference, pp 38–39Google Scholar
  26. 26.
    Warner K, Oakley DC, Donnelly JP, Keast CL, Shaver DC (2006) Layer transfer of FDSOI CMOS to 150 mm InP substrates for mixed-material integration. In: International conference on indium phosphide related materials, pp 226–228Google Scholar
  27. 27.
    Aull B, Burns J, Chen C, Felton B, Hanson H, Keast C, Knecht J, Loomis A, Renzi M, Soares A, Suntharalingam V, Warner K, Wolfson D, Yost D, Young D (2006) Laser radar imager based on three-dimensional integration of Geiger-mode avalance photodiodes with two SOI timing-circuit layers. In Digest of technical Papers. IEEE international solid-state circuits conference, pp 304–305Google Scholar

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© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Lincoln LaboratoryMassachusetts Institute of TechnologyLexingtonUSA

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