Optimum Reverse Body Biasing for Leakage Minimization

  • Nikhil Jayakumar
  • Suganth Paul
  • Rajesh Garg
  • Kanupriya Gulati
  • Sunil P. Khatri


One of the methods to reduce leakage power is by increasing the threshold voltages (V T) of the device. This is done either statically, through use of multi-threshold devices or dynamically, through Reverse Body Biasing (RBB).

The sub-threshold leakage (cut-off) current of a transistor decreases with greater applied RBB. Reverse Body Biasing affects V T through body effect, and subthreshold leakage has an exponential dependence on V T, as we have discussed earlier.

However, while the sub-threshold leakage decreases, there are other components to the leakage current that have to be considered as well. Two of these are bulk Band-to-Band-Tunneling (BTBT) and surface BTBT. Bulk BTBT is commonly referred to as simply BTBT while surface BTBT is commonly called Gate Induced Drain Leakage (GIDL) [2, 8]. While GIDL does not play a major role at RBB [2], BTBT increases with applied RBB [2, 5, 6, 9]. This means that there is an optimum RBB voltage at which the total leakage power (the sum of the sub-threshold leakage, the gate leakage, BTBT and GIDL) is minimum [2,5,6,9]. In modern processes this optimum point is reached before the upper limit of the RBB (based on the voltage at which the bulk-drain/bulk-source junction breaks down). Also, this optimum point can vary with temperature and process variations. In this chapter we show that it is desirable to operate at the optimal RBB point that minimizes total leakage.We present a scheme that monitors the total leakage current (the sum of the sub-threshold, BTBT and gate leakage) of an IC with a representative leaking device and, using this monitored value, we automatically find the optimum RBB value across temperature and process corners, using a self-adjusting circuit. Our approach has a modest placed-and-routed area utilization and a low power consumption. In Sect. 7.2 we discuss the motivation behind our work. Section 7.3 discusses previous approaches to dynamically adjust body bias. Section 7.4 describes our approach to dynamically self-adjust the RBB of PMOS and NMOS devices in order to obtain a minimum total leakage, along with experimental results that support the utility of our scheme.


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  1. 1.
    Chen, J., Wong, S., Wang, Y.: An Analytic Three-Terminal Band-to-Band Tunneling Model on GIDL in MOSFET. IEEE Transactions on Electron Devices 48(7), 1400–1405 (2001)CrossRefGoogle Scholar
  2. 2.
    Keshavarzi, A., Narendra, S., Borkar, S., Hawkins, C., Royi, K., De, V.: Technology Scaling Behavior of Optimum Reverse Body Bias for Standby Leakage Power Reduction in CMOS ICs. In: Proc. International Symposium on Low Power Electronics and Design, pp. 252–254. San Diego, CA (1999)Google Scholar
  3. 3.
    Kobayashi, T., Sakurai, T.: Self-adjusting Threshold-Voltage Scheme (SATS) for Low-Voltage High-Speed Operation. In: Proc. IEEE Custom Integrated Circuits Conference, pp. 271–274. San Diego, CA (1994)Google Scholar
  4. 4.
    Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T., Yoshioka, S., Suzuki, K., Sano, F., Norishima, M., Murota, M., Kako, M., Kakumu, M.K.M., Sakurai, T.: A 0.9-V, 150-MHz, 10-mW, 4 mm 2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme. IEEE Journal of Solid-State Circuits 31(11), 1770–1779 (1996)Google Scholar
  5. 5.
    Lin, Y.S., Wu, C.C., Chang, C.S., Yang, R.P., Chen, W.M., Liaw, J.J., Diaz, C.: Leakage Scaling in Deep Submicron CMOS for SoC. IEEE Transactions on Electron Devices 49(6), 1034–1041 (2002)CrossRefGoogle Scholar
  6. 6.
    Liu, X., Mourad, S.: Performance of Submicron CMOS Devices and Gates with Substrate Biasing. In: The IEEE International Symposium on Circuits and Systems, vol. 4, pp. 9–12. Geneva, Switzerland (2000)Google Scholar
  7. 7.
    Mukhopadhyay, S., Mahmoodi-Meimand, H., Neau, C., Roy, K.: Leakage in Nanometer Scale CMOS Circuits. In: Proc. International Symposium on VLSI Technology, Systems, and Applications, pp. 307–312. Hsinchu, Taiwan (2003)Google Scholar
  8. 8.
    Neau, C.: Personal communication (2004)Google Scholar
  9. 9.
    Neau, C., Roy, K.: Optimal Body Bias Selection for Leakage Improvement and Process Compensation over Different Technology Generations. In: Proc. International Symposium on Low Power Electronics and Design, pp. 116 – 121. Seoul, Korea (2003)Google Scholar
  10. 10.
    Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proc. IEEE 91(2), 305–327 (2003)CrossRefGoogle Scholar
  11. 11.
    Soeleman, H., Roy, K., Paul, B.: Robust Subthreshold Logic for Ultra-low Power Operation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9(1), 90–99 (2001)Google Scholar
  12. 12.
    Taur, Y., Ning, T.H.: Fundamentals of Modern VLSI Devices. Cambridge University Press, New York, NY (1998)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Nikhil Jayakumar
    • 1
  • Suganth Paul
    • 2
  • Rajesh Garg
    • 3
  • Kanupriya Gulati
    • 4
  • Sunil P. Khatri
    • 5
  1. 1.SunnyvaleUSA
  2. 2.AustinUSA
  3. 3.HillsboroUSA
  4. 4.College StationUSA
  5. 5.Dept. Electrical & Computer EngineeringTexas A & M UniversityCollege StationUSA

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