Abstract
In recent times, leakage power reduction has received much attention in academia as well as industry. Several means of reducing leakage power have been proposed. Some of these are mentioned here.
One of the natural techniques to reduce the leakage of a circuit is to gate the power supply using power-gating transistors (also called sleep transistors). Typically high- V T power-gating transistors are placed between the power supplies and the logic gates. This is called the MTCMOS (Multi-threshold CMOS) approach [14, 17]. In standby, these power-gating transistors are turned off, thus shutting off power to the gates of the circuit. The MTCMOS approach can reduce circuit leakages by up to 2–3 orders of magnitude (depending on the threshold voltages and size of the sleep transistors used). However, the addition of sleep transistors causes an increase in the delay of the circuit. This delay penalty can be reduced by appropriately sizing up the sleep transistor. The downside to the up-sizing of the sleep transistor is the accompanied increase in the time and switching energy spent in waking up the circuit. As a consequence, power-gating (turning off the sleep transistors) is applied only when the circuit is expected to be in the standby state for a long period of time and when the wake-up time is tolerable. If a circuit using power-gating/sleep transistors goes in and comes out of the standby state too often, the power consumptionmay actually increase due to the higher power consumed in waking up the circuit. Another disadvantage of the MTCMOS approach is the fact that implementation of this technique requires circuit modification and possibly additional process steps (since high-V T sleep transistors are used). Also, since cell inputs and outputs as well as bulk nodes float in an MTCMOS design operating in standby mode, the precise prediction or control of leakage is extremely difficult in MTCMOS. The voltage of these floating nodes can significantly affect the device threshold voltages. Hence, it is very difficult to precisely predict or control leakage in MTCMOS designs. Another drawback of MTCMOS is that memory elements in MTCMOS would require clean power supplies routed to them if we want to maintain their state in standby mode [17].
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Jayakumar, N., Paul, S., Garg, R., Gulati, K., Khatri, S.P. (2010). Existing Leakage Minimization Approaches. In: Minimizing and Exploiting Leakage in VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0950-3_2
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