Reclaiming the Sub-threshold Speed Penalty Through Micropipelining

  • Nikhil Jayakumar
  • Suganth Paul
  • Rajesh Garg
  • Kanupriya Gulati
  • Sunil P. Khatri


Sub-threshold circuit design is an appealing means to dramatically reduce power consumption. However, sub-threshold designs suffer from the drawback of being significantly slower than traditional designs. To reduce the speed gap between sub-threshold and traditional designs, we propose a sub-threshold circuit design approach based on asynchronous micropipelining of a levelized network of PLAs.We describe the handshaking protocol, circuit design and logic synthesis issues in this context. Our preliminary results demonstrate that by using our approach, a design can be sped up by about 7×, with an area penalty of 47%. Further, our approach yields an energy improvement of about 4×, compared to a traditional network of PLA design. Our approach is quite general and can be applied to traditional circuits as well.

The key contribution of this work is to come up with a technique that enjoys an extreme low power consumption due to the use of sub-threshold circuitry, but at the same time compensates for the sub-threshold delay penalty. Such techniques would widen the applicability of sub-threshold circuit design approaches to a broader class of applications. The proposed approach utilizes a network of PLA (NPLA) based sub-threshold circuit design approach, configured in an asynchronous micropipelined structure to enhance the speed of the circuit. Sub-threshold circuit design has so far been used in only simple digital circuits and analog circuits. The design methodologies used in implementing such circuits are adhoc. Our approach provides a systematic EDA framework for the design of complex digital systems using sub-threshold NPLA circuits. It additionally utilizes an asynchronous micropipelining approach to speed up the sub-threshold design. Our experiments indicate that this approach yields a significant circuit speedup and improvement in energy consumption compared to traditionalNPLA designs. Circuit speedup is measured in terms of computational throughput. In Sect. 12.2, we provide details about our micropipelined PLA-based asynchronous protocol and the logic synthesis approach to decompose a circuit into this circuit paradigm. The delay, area, power and energy characteristics of designs, which are implemented using our approach, are given in Sect. 12.3.


Output Line Traditional Design Traditional Network Logic Synthesis Handshaking Protocol 


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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Nikhil Jayakumar
    • 1
  • Suganth Paul
    • 2
  • Rajesh Garg
    • 3
  • Kanupriya Gulati
    • 4
  • Sunil P. Khatri
    • 5
  1. 1.SunnyvaleUSA
  2. 2.AustinUSA
  3. 3.HillsboroUSA
  4. 4.College StationUSA
  5. 5.Dept. Electrical & Computer EngineeringTexas A & M UniversityCollege StationUSA

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