Adaptive Body Biasing to Compensate for PVT Variations

  • Nikhil Jayakumar
  • Suganth Paul
  • Rajesh Garg
  • Kanupriya Gulati
  • Sunil P. Khatri
Chapter

Abstract

One of the main disadvantages of their sub-threshold circuits is their extreme sensitivity to variations in power supply, temperature and processing. In this chapter, we present a sub-threshold design methodology that automatically self-adjusts for inter and intra-die process, supply voltage and temperature (PVT) variations. This adjustment is achieved by performing bulk voltage adjustments in a closed-loop fashion. The design methodology uses medium-sized Programmable Logic Arrays (PLAs) as the circuit implementation structure. Details about the structure and operation of the PLAs are presented in Sect. 10.3. The design has a global beat clock to which the delay of a spatially localized cluster of PLAs is “phase locked”. The synchronization is performed in a closed-loop fashion, using a phase detector and a charge pump that drives the bulk nodes of the PLAs in the cluster. The details of this scheme are presented in Sect. 10.4. The experimental results presented in Sect. 10.5 demonstrate that our technique is able to dynamically phase lock the PLA delays to the beat clock, across a wide range of PVT variations, enabling the sub-threshold design methodology to be applicable in practice. We also present an analysis of the loop gain of this closed-loop adaptive body biasing technique in Sect. 10.6.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Aguiav, R.L., Santos, D.M.: Modelling Charge-Pump Delay Locked Loops. In: Proc. International Conference on Electronics, Circuits and Systems, pp. 823–826. Pafos, Cyprus (1999)Google Scholar
  2. 2.
    Cao, Y., Sato, T., Sylvester, D., Orshansky, M., Hu, C.: New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design. In: Proc. IEEE Custom Integrated Circuit Conference, pp. 201–204. Orlando, FL (2000). http://www-device.eecs.berkeley.edu/~ptm
  3. 3.
    Jayakumar, N., Khatri, S.: A METAL and VIA Maskset Programmable VLSI Design Methodology Using PLAs. In: Proc. IEEE/ACM International Conference on Computer Aided Design, pp. 590–594. San Jose, CA (2004)Google Scholar
  4. 4.
    Khatri, S., Mehrotra, A., Brayton, R., Sangiovanni-Vincentelli, A., Otten, R.: A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. In: Proc. Design Automation Conference. New Orleans, LA (1999)Google Scholar
  5. 5.
    Khatri, S.P., Brayton, R.K., Sangiovanni-Vincentelli, A.: Cross-talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. In: Proc. IEEE/ACM International Conference on Computer Aided Design, pp. 412–418. San Jose, CA (2000)Google Scholar
  6. 6.
    Nagel, L.: SPICE: A Computer Program to Simulate Computer Circuits. In: University of California, Berkeley UCB/ERL Memo M520 (1995)Google Scholar
  7. 7.
    Paul, B., Soeleman, H., Roy, K.: An 8X8 Sub-Threshold Digital CMOS Carry Save Array Multiplier. In: Proc. European Solid State Circuits Conference, pp. 377–380. Villach, Austria (2001)Google Scholar
  8. 8.
    Soeleman, H., Roy, K.: Ultra-low Power Digital Subthreshold Logic Circuits. In: Proc. International Symposium on Low Power Electronic Design, pp. 94–96. San Diego, CA (1999)Google Scholar
  9. 9.
    Soeleman, H., Roy, K.: Digital CMOS Logic Operation in the Sub-threshold Region. In: Proc. Tenth Great Lakes Symposium on VLSI, pp. 107–112. Chicago, IL (2000)Google Scholar
  10. 10.
    Soeleman, H., Roy, K., Paul, B.: Robust Subthreshold Logic for Ultra-low Power Operation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9(1), 90–99 (2001)Google Scholar
  11. 11.
    Tschanz, J., Kao, J., Narendra, S., Nair, R., Antoniadis, D., Chandrakasan, A., De, V.: Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-die Parameter Variations on Microprocessor Frequency and Leakage 37, 1396–1402 (2002)Google Scholar
  12. 12.
    Zarkesh-Ha, P., Mule, T., Meindl, J.D.: Characterization and Modelling of Clock Skew with Process Variation. In: Proc. IEEE Custom Integrated Circuits Conference, pp. 441–444. San Diego, CA (1999)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Nikhil Jayakumar
    • 1
  • Suganth Paul
    • 2
  • Rajesh Garg
    • 3
  • Kanupriya Gulati
    • 4
  • Sunil P. Khatri
    • 5
  1. 1.SunnyvaleUSA
  2. 2.AustinUSA
  3. 3.HillsboroUSA
  4. 4.College StationUSA
  5. 5.Dept. Electrical & Computer EngineeringTexas A & M UniversityCollege StationUSA

Personalised recommendations