• Nikhil Jayakumar
  • Suganth Paul
  • Rajesh Garg
  • Kanupriya Gulati
  • Sunil P. Khatri


Since the advent of CMOS technology, an increased number of transistors per die and greater performance have been the primary driving factors for the semiconductor industry and process technology. The ability to integrate more transistors per die allowed chip manufacturers to put more components of a system into a single package and thus reduce not only just the sizes of the electronic devices we use today but also the cost and delay. The intense competition in the semiconductor industry has forced chip manufacturers pursue these goals aggressively. To the credit of the semiconductor industry, these goals (more transistors per die and greater performance) have been growing at an exponential rate, following Moore’s law. However, in the process, the power dissipation of the Integrated Circuit (IC) has been growing at an alarming rate as well. In recent times, the excessive power consumption of contemporary circuits has become a dominant design concern [2]. In fact, the issue of power dissipation is one of the main concerns that has hampered the further scaling of transistors. A Very Large Scale Integrated (VLSI) chip consists of many energy storage elements, mainly capacitors, some that are required for computation (MOSFET device capacitances) and some that are a hindrance to circuit operation (parasitic capacitances). These capacitors are continually charged and discharged through resistive elements during circuit operation, resulting in energy dissipation in the form of heat. The amount of heat dissipated puts a restriction on the computational performance of the circuit, or the number of times the transistors in the circuit can switch for a given power budget. One could argue that the shrinking of devices has reduced the amount of parasitic capacitance and this alleviates power dissipation problems. However, the increase in the number of devices due to the increase in device density has more than compensated for the decrease in the parasitic capacitance of a single device.


Power Dissipation Parasitic Capacitance Very Large Scale Integrate Leakage Power Gate Leakage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Microprocessor Power Consumption. Accessed on 5th May, 2005
  2. 2.
    The International Technology Roadmap for Semiconductors. (2003). Accessed on 12th Nov, 2003
  3. 3.
    Daasch, W., Lim, C., Cai, G.: Design of VLSI CMOS Circuits Under Thermal Constraint. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 49(8), 589–593 (2002)CrossRefGoogle Scholar
  4. 4.
    Rabaey, J.: Digital Integrated Circuits: A Design Perspective. Prentice Hall Electronics and VLSI Series. Prentice Hall, Upper Saddle River, NJ (1996)Google Scholar
  5. 5.
    Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proc. IEEE 91(2), 305–327 (2003)CrossRefGoogle Scholar
  6. 6.
    Weste, N., Eshraghian, K.: Principles of CMOS VLSI Design - A Systems Perspective. Addison-Wesley, Reading, MA (1988)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Nikhil Jayakumar
    • 1
  • Suganth Paul
    • 2
  • Rajesh Garg
    • 3
  • Kanupriya Gulati
    • 4
  • Sunil P. Khatri
    • 5
  1. 1.SunnyvaleUSA
  2. 2.AustinUSA
  3. 3.HillsboroUSA
  4. 4.College StationUSA
  5. 5.Dept. Electrical & Computer EngineeringTexas A & M UniversityCollege StationUSA

Personalised recommendations