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Fault Table Generation Using Graphics Processors

  • Kanupriya Gulati
  • Sunil P. Khatri
Chapter

Abstract

In this chapter, we explore the implementation of fault table generation on a graphics processing unit (GPU). A fault table is essential for fault diagnosis and fault detection in VLSI testing and debug. Generating a fault table requires extensive fault simulation, with no fault dropping, and is extremely expensive from a computational standpoint.

Keywords

Graphic Processing Unit Global Memory Test Vector Thread Block Single Instruction Multiple Data 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    NVIDIA Tesla GPU Computing Processor. http://www.nvidia.com/object/IO_43499.html
  2. 2.
  3. 3.
    Abramovici, A., Levendel, Y., Menon, P.: A logic simulation engine. In: IEEE Transactions on Computer-Aided Design, vol. 2, pp. 82–94 (1983)Google Scholar
  4. 4.
    Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital Systems Testing and Testable Design. Computer Science Press, New York (1990)Google Scholar
  5. 5.
    Abramovici, M., Menon, P.R., Miller, D.T.: Critical path tracing – An alternative to fault simulation. In: DAC ’83: Proceedings of the 20th Conference on Design Automation, pp. 214–220. IEEE Press, Piscataway, NJ (1983)Google Scholar
  6. 6.
    Agrawal, P., Dally, W.J., Fischer, W.C., Jagadish, H.V., Krishnakumar, A.S., Tutundjian, R.: MARS: A multiprocessor-based programmable accelerator. IEEE Design and Test 4(5), 28–36 (1987)CrossRefGoogle Scholar
  7. 7.
    Amin, M.B., Vinnakota, B.: Workload distribution in fault simulation. Journal of Electronic Testing 10(3), 277–282 (1997)CrossRefGoogle Scholar
  8. 8.
    Antreich, K., Schulz, M.: Accelerated fault simulation and fault grading in combinational circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6(5), 704–712 (1987)CrossRefGoogle Scholar
  9. 9.
    Banerjee, P.: Parallel Algorithms for VLSI Computer-aided Design. Prentice Hall Englewood Cliffs, NJ (1994)Google Scholar
  10. 10.
    Beece, D.K., Deibert, G., Papp, G., Villante, F.: The IBM engineering verification engine. In: DAC ’88: Proceedings of the 25th ACM/IEEE Conference on Design Automation, pp. 218–224. IEEE Computer Society Press, Los Alamitos, CA (1988)Google Scholar
  11. 11.
    Bossen, D.C., Hong, S.J.: Cause-effect analysis for multiple fault detection in combinational networks. IEEE Transactions on Computers 20(11), 1252–1257 (1971)MATHCrossRefGoogle Scholar
  12. 12.
    Gulati, K., Khatri, S.P.: Fault table generation using graphics processing units. In: IEEE International High Level Design Validation and Test Workshop (2009)Google Scholar
  13. 13.
    Harel, D., Sheng, R., Udell, J.: Efficient single fault propagation in combinational circuits. In: Proceedings of the International Conference on Computer-Aided Design ICCAD, pp. 2–5 (1987)Google Scholar
  14. 14.
    Hong, S.J.: Fault simulation strategy for combinational logic networks. In: Proceedings of Eighth International Symposium on Fault-Tolerant Computing, pp. 96–99 (1979)Google Scholar
  15. 15.
    Lee, H.K., Ha, D.S.: An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagation. In: Proceedings of the IEEE International Test Conference on Test, pp. 946–955. IEEE Computer Society, Washington, DC (1991)Google Scholar
  16. 16.
    Mueller-Thuns, R., Saab, D., Damiano, R., Abraham, J.: VLSI logic and fault simulation on general-purpose parallel computers. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 446–460 (1993)Google Scholar
  17. 17.
    Narayanan, V., Pitchumani, V.: Fault simulation on massively parallel simd machines: Algorithms, implementations and results. Journal of Electronic Testing 3(1), 79–92 (1992)CrossRefGoogle Scholar
  18. 18.
    Ozguner, F., Daoud, R.: Vectorized fault simulation on the Cray X-MP supercomputer. In: Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers, IEEE International Conference on, pp. 198–201 (1988)Google Scholar
  19. 19.
    Parkes, S., Banerjee, P., Patel, J.: A parallel algorithm for fault simulation based on PROOFS. pp. 616–621. URL citeseer.ist.psu.edu/article/parkes95parallel.html
  20. 20.
    Pfister, G.F.: The Yorktown simulation engine: Introduction. In: DAC ’82: Proceedings of the 19th Conference on Design Automation, pp. 51–54. IEEE Press, Piscataway, NJ (1982)Google Scholar
  21. 21.
    Pomeranz, I., Reddy, S., Tangirala, R.: On achieving zero aliasing for modeled faults. In: Proc. [3rd] European Conference on Design Automation, pp. 291–299 (1992)Google Scholar
  22. 22.
    Pomeranz, I., Reddy, S.M.: On the generation of small dictionaries for fault location. In: ICCAD ’92: 1992 IEEE/ACM International Conference Proceedings on Computer-Aided Design, pp. 272–279. IEEE Computer Society Press, Los Alamitos, CA (1992)Google Scholar
  23. 23.
    Pomeranz, I., Reddy, S.M.: A same/different fault dictionary: An extended pass/fail fault dictionary with improved diagnostic resolution. In: DATE ’08: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1474–1479 (2008)Google Scholar
  24. 24.
    Richman, J., Bowden, K.R.: The modern fault dictionary. In: Proceedings of the International Test Conference, pp. 696–702 (1985)Google Scholar
  25. 25.
    Tai, S., Bhattacharya, D.: Pipelined fault simulation on parallel machines using the circuitflow graph. In: Computer Design: VLSI in Computers and Processors, pp. 564–567 (1993)Google Scholar
  26. 26.
    Tulloss, R.E.: Fault dictionary compression: Recognizing when a fault may be unambiguously represented by a single failure detection. In: Proceedings of the Test Conference, pp. 368–370 (1980)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.CoppellUSA
  2. 2.Department of Electrical & Computer EngineeringTexas A & M UniversityCollege StationUSA

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