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Accelerating statistical static Timing Analysis Using Graphics Processors

Chapter

Abstract

In this chapter,we explore the implementation of Monte Carlo based statistical static timing analysis (SSTA) on a graphics processing unit (GPU). SSTA via Monte Carlo simulations is a computationally expensive, but important step required to achieve design timing closure. It provides an accurate estimate of delay variations and their impact on design yield.

Keywords

Graphic Processing Unit Global Memory Single Instruction Multiple Data Delay Distribution Texture Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
  2. 2.
  3. 3.
  4. 4.
  5. 5.
  6. 6.
  7. 7.
  8. 8.
    Agarwal, A., Blaauw, D., Zolotov, V.: Statistical timing analysis for intra-die process variations with spatial correlations. In: Proceedings of the International Conference on Computer-Aided Design, pp. 900–907 (2003)Google Scholar
  9. 9.
    Agarwal, A., Blaauw, D., Zolotov, V., Vrudhula, S.: Statistical timing analysis using bounds. In: Proceedings of the Conference on Design Automation and Test in Europe, pp. 62–67 (2003)Google Scholar
  10. 10.
    Agarwal, A., Zolotov, V., Blaauw, D.T.: Statistical timing analysis using bounds and selective enumeration. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, pp. 1243–1260 (2003)Google Scholar
  11. 11.
    Benkoski, J., Strojwas, A.J.: A new approach to hierarchical and statistical timing simulations. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, pp. 1039–1052 (1987)Google Scholar
  12. 12.
    C, C.V., Ravindran, K., Kalafala, K., Walker, S.G., Narayan, S.: First-order incremental block-based statistical timing analysis. In: Proceedings of the Design Automation Conference, pp. 331–336 (2004)Google Scholar
  13. 13.
    Cabaleiro, J., Carazo, J., Zapata, E.: Parallel algorithm for principal component analysis based on Hotelling procedure. In: Proceedings of EUROMICRO Workshop On Parallel and Distributed Processing, pp. 144–149 (1993)Google Scholar
  14. 14.
    Chang, H., Sapatnekar, S.S.: Statistical timing analysis under spatial correlations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(9), 1467–1482 (2005)CrossRefGoogle Scholar
  15. 15.
    Devgan, A., Kashyap, C.V.: Block-based static timing analysis with uncertainty. In: Proceedings of the International Conference on Computer-Aided Design, pp. 607–614 (2003)Google Scholar
  16. 16.
    Garg, R., Jayakumar, N., Khatri, S.P.: On the improvement of statistical timing analysis. International Conference on Computer Design pp. 37–42 (2006)Google Scholar
  17. 17.
    Gulati, K., Khatri, S.P.: Accelerating statistical static timing analysis using graphics processing units. In: Proceedings, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 260–265 (2009)Google Scholar
  18. 18.
    Heras, D., Cabaleiro, J., Perez, V., Costas, P., Rivera, F.: Principal component analysis on vector computers. In: Proceedings of VECPAR, pp. 416–428 (1996)Google Scholar
  19. 19.
    Jyu, H.F., Malik, S.: Statistical delay modeling in logic design and synthesis. In: Proceedings of the Design Automation Conference, pp. 126–130 (1994)Google Scholar
  20. 20.
    Le, J., Li, X., Pileggi, L.T.: STAC: Statistical timing analysis with correlation. In: DAC ’04: Proceedings of the 41st annual conference on Design automation, pp. 343–348 (2004)Google Scholar
  21. 21.
    Liou, J.J., Cheng, K.T., Kundu, S., Krstic, A.: Fast statistical timing analysis by probabilistic event propagation. In: Proceedings of the Design Automation Conference, pp. 661–666 (2001)Google Scholar
  22. 22.
    Matsumoto, M., Nishimura, T.: Mersenne twister: A 623-dimensionally equidistributed uniform pseudo-random number generator. ACM Transactions on Modeling, and Computer Simulation 8(1), 3–30 (1998)MATHCrossRefGoogle Scholar
  23. 23.
    Matsumoto, M., Nishimura, T.: Monte Carlo and Quasi-Monte Carlo Methods, chap. Dynamic Creation of Pseudorandom Number Generators, pp. 56–69. Springer, New York (1998)Google Scholar
  24. 24.
    McGeer, P., Saldanha, A., Brayton, R., Sangiovanni-Vincentelli, A.: Logic Synthesis and Optimization, chap. Delay Models and Exact Timing Analysis, pp. 167–189. Kluwer Academic Publishers, Dordrecht (1993)Google Scholar
  25. 25.
    Nitta, I., Shibuya, T., Homma, K.: Statistical static timing analysis technology. FUJITSU Scientific and Technical Journal 43(4), 516–523 (2007)Google Scholar
  26. 26.
    Sentovich, E.M., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P.R., Brayton, R.K., Sangiovanni-Vincentelli, A.L.: SIS: A System for Sequential Circuit Synthesis. Technical Report UCB/ERL M92/41, Electronics Research Laboratory, University of California, Berkeley, CA 94720 (1992)Google Scholar
  27. 27.
    Zhang, L., Chen, W., Hu, Y., Chen, C.C.P.: Statistical timing analysis with extended pseudo-canonical timing model. In: DATE ’05: Proceedings of the conference on Design, Automation and Test in Europe, pp. 952–957 (2005)Google Scholar

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© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.CoppellUSA
  2. 2.Department of Electrical & Computer EngineeringTexas A & M UniversityCollege StationUSA

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