Accelerating Boolean Satisfiability on a Custom IC

  • Kanupriya Gulati
  • Sunil P. Khatri


Boolean satisfiability (SAT) is a core NP-complete problem. Several heuristic software and hardware approaches have been proposed to solve this problem. In this work, we present a hardware solution to the SAT problem.We propose a custom IC to implement our approach, in which the traversal of the implication graph as well as conflict clause generation is performed in hardware, in parallel.


Hardware Architecture Terminal Cell Very Large Scale Integration Communication Unit Clause Generation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.CoppellUSA
  2. 2.Department of Electrical & Computer EngineeringTexas A & M UniversityCollege StationUSA

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