Abstract
This chapter presents the sensitizable statistical timing analysis (StatSense) methodology, developed to remove the pessimism due to two sources of inaccuracy, which plague current statistical static timing analysis (SSTA) tools. Specifically, the StatSense approach implicitly eliminates false paths, and also uses different delay distributions for different input transitions for any gate. StatSense consists of two phases. In the first phase, a set of N logically sensitizable vector transitions which result in the largest delays for a circuit are obtained. In the second phase, these delay-critical sensitizable input vector transitions are propagated using a Monte-Carlo-based technique, to obtain the delay distribution at the outputs of the design. The specific input transitions at any gate are known after the first phase. The second phase performs Monte-Carlo-based SSTA, using the appropriate gate delay distribution corresponding to the particular input transition for each gate. The StatSense approach is able to significantly improve the accuracy of SSTA analysis. The circuit delay distribution obtained using StatSense closely matches with that obtained by SPICE-based Monte-Carlo simulations.
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References
M. Orshansky, S. R. Nassif, and D. Boning, Design for manufacturability and statistical design: A constructive approach, US Springer, 2008.
K. Agarwal and S. Nassif, “Characterizing process variation in nanometer CMOS,” in Proc. of the Design Automation Conf., June 2007, pp. 396–399.
K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer, “High-performance CMOS variability in the 65-nm regime and beyond,” IBM Journal of Research and Development, vol. 50, pp. 433–449, July/Sept. 2006.
H. Chang and S. S. Sapatnekar, “Statistical timing analysis under spatial correlations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 9, pp. 1467–1482, Sept. 2005.
J. Benkoski and A. J. Strojwas, “A new approach to hierarchical and statistical timing simulations,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov. 1987, vol. 6, pp. 1039–1052.
H. Jyu and S. Malik, “Statistical delay modeling in logic design and synthesis,” in Proc. of the Design Automation Conf., 1994, pp. 126–130.
C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, “First-order incremental block-based statistical timing analysis,” in Proc. of the Design Automation Conf., 2004, pp. 331–336.
A. Agarwal, V. Zolotov, and D. T. Blaauw, “Statistical timing analysis using bounds and selective enumeration,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Sept. 2003, vol. 22, pp. 1243–1260.
A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process variations with spatial correlations,” in Proc. of the Intl. Conf. on Computer-Aided Design, Nov. 2003, pp. 900–907.
A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, “Statistical timing analysis using bounds,” in Proc. of the Conf. on Design Automation and Test in Europe, March.
A. Devgan and C. V. Kashyap, “Block-based static timing analysis with uncertainty,” in Proc. of the Intl. Conf. on Computer-Aided Design, 2003, pp. 607–614.
J. Liou, K. Cheng, S. Kundu, and A. Krstic, “Fast statistical timing analysis by probabilistic event propagation,” in Proc. of the Design Automation Conf., 2001, pp. 661–666.
J. Liou, A. Krstic, L. Wang, and K. Cheng, “False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation,” in Proc. of the Design Automation Conf., 2002, pp. 566–569.
L. Xie and A. Davoodi, “Bound-based identification of timing-violating paths under variability,” in Proc. of the Asia and South Pacific Design Automation Conf., Jan. 2009, pp. 278–283.
P. McGeer, A. Saldanha, R. Brayton, and A. Sangiovanni-Vincentelli, Logic Synthesis and Optimization, chapter Delay Models and Exact Timing Analysis, pp. 167–189, US Kluwer Academic Publishers, Boston, MA, 1993.
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “SIS: A system for sequential circuit synthesis,” Tech. Rep. UCB/ERL M92/41, Electronics Research Laboratory, Univ. of California, Berkeley, May 1992.
S. A. Cook, “The complexity of theorem-proving procedures,” in Proc. of the Third Annual ACM Symposium on Theory of Computing, 1971, pp. 151–158.
M. Davis, G. Logemann, and D. Loveland, “A machine program for theorem-proving,” Communication of the ACM, vol. 5, no. 7, pp. 394–397, 1962.
S. Malik, Y. Zhao, C. F. Madigan, L. Zhang, and M. W. Moskewicz, “Chaff: Engineering an efficient SAT solver,” in Proc. of the Design Automation Conf., 2001, pp. 530–535.
Y. Kukimoto, W. Gosti, A. Saldanha, and R. K. Brayton, “Approximate timing analysis of combinational circuits under the XBD0 model,” in Proc. of the Intl. Conf. on Computer-Aided Design, 1997, pp. 176–181.
L. Nagel, “Spice: A computer program to simulate computer circuits,” in University of California, Berkeley UCB/ERL Memo M520, May 1995.
Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “New paradigm of predictive MOSFET and interconnect modeling for early circuit design,” in Proc. of IEEE Custom Integrated Circuit Conf., June 2000, pp. 201–204.
M. C. T. Chao, L. Wang, K. Cheng, and S. Kundu, “Static statistical timing analysis for latch-based pipeline designs,” in Proc. of the Intl. Conf. on Computer-Aided Design, 2004, pp. 468–472.
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Garg, R., Khatri, S.P. (2010). Sensitizable Statistical Timing Analysis. In: Analysis and Design of Resilient VLSI Circuits. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0931-2_8
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