Split-output-based Radiation Tolerant Circuit Design Approach
In this chapter, another radiation tolerant combinational circuit design approach is presented for combinational designs. This approach is called the split-output-based hardening approach. This hardening approach exploits the fact that if a gate is implemented using only PMOS (NMOS) transistors, then a radiation particle strike can result only in logic 0–1 (1–0) transients. Based on this observation, radiation hardened variants of regular static CMOS gates are derived. Split-output-based radiation hardened gates exhibit an extremely high degree of radiation tolerance, which is validated at the circuit level. Hence, this approach is suitable for hardening against medium and high energy radiation particles. Using these split-output gates, circuit level hardening is performed based on logical masking, to selectively harden those gates in a circuit, which contribute maximally to the soft error failure rate of the circuit. The gates whose outputs have a low probability of being logically masked are replaced by their radiation tolerant counterparts, such that the digital design achieves a soft error rate reduction of a desired amount (typically 90%). The split-output-based hardening approach is able to harden combinational circuits with a modest layout area and delay penalty.
KeywordsSoft Error NMOS Transistor PMOS Transistor Node Voltage Critical Charge
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