3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits



An analysis of the effects of voltage scaling on the radiation tolerance of VLSI systems is presented in this chapter. For this analysis, 3D simulations of radiation particle strikes on the output of an inverter (implemented using DVS and subthreshold design) were performed. The radiation particle strike on an inverter was simulated using Sentaurus-DEVICE for different inverter sizes, inverter loads, supply voltage values, and the energy of the radiation particles. From these 3D simulations, several nonintuitive observations were made, which are important to consider during radiation hardening of such DVS and subthreshold circuits. On the basis of these observations, several guidelines are proposed for radiation hardening of such designs. These guidelines suggest that traditional radiation hardening approaches need to be revisited for DVS and subthreshold designs. A charge collection model for DVS circuits is also proposed, using the results of these 3D simulations. The parameters of this charge collection model can be included in transistor model cards in SPICE, to improve the accuracy of SPICE-based simulations of radiation events in DVS circuits.


Supply Voltage Charge Collection Radiation Particle NMOS Transistor PMOS Transistor 
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  1. 1.
    ITRS, “The international technology roadmap for semiconductors edition,” Available: http://public.itrs.net/, 2003
  2. 2.
    R. Gonzalez, B. M. Gordon, and M. A. Horowitz, “Supply and threshold voltage scaling for low power CMOS,” IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1210–1216, Aug 1997.CrossRefGoogle Scholar
  3. 3.
    T. Burd, T. Pering, A. Stratakos, and T. Brodersen, “A dynamic voltage scaled microprocessor system,” in Proc. of the Intl. Solid State Circuits Conf., 2000, pp. 294–295, 466.Google Scholar
  4. 4.
    K. Flautner, S. Reinhardt, and T. Mudge, “Automatic performance setting for dynamic voltage scaling,” Wireless Networks, vol. 8, no. 5, pp. 507–520, 2002.MATHCrossRefGoogle Scholar
  5. 5.
    W. Kim, D. Shin, H. S. Yun, J. Kim, and S. L. Min, “Performance comparison of dynamic voltage scaling algorithms for hard real-time systems,” in Proc. of the Symposium on Real-Time and Embedded Technology and Applications, 2002, pp. 219–228.Google Scholar
  6. 6.
    B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, “Theoretical and practical limits of dynamic voltage scaling,” in Proc. of the Design Automation Conf., 2004, pp. 868–873.Google Scholar
  7. 7.
    C. Duan and S. P. Khatri, “Computing during supply voltage switching in DVS enabled real-time processors,” in Proc. of the Intl. Symposium on Circuits and Systems, May 2006, pp. 5115–5118.Google Scholar
  8. 8.
    S. Choi, B. Kim, J. Park, C. Kang, and D. Eom, “An implementation of wireless sensor network,” IEEE Transactions on Consumer Electronics, vol. 50, no. 1, pp. 236–244, Feb 2004.CrossRefGoogle Scholar
  9. 9.
    A. Abidi, G. Pottie, and W. Kaiser, “Power-conscious design of wireless circuits and systems,” Proceedings of the IEEE, vol. 88, no. 10, pp. 1528–1545, Oct 2000.CrossRefGoogle Scholar
  10. 10.
    N. Jayakumar, R. Garg, B. Gamache, and S. P. Khatri, “A PLA based asynchronous micropipelining approach for subthreshold circuit design,” in Proc. of the Design Automation Conf., July 2006, pp. 419–424.Google Scholar
  11. 11.
    Synopsys Inc., Mountain View, CA, Sentaurus user’s manuals, 2007.12 edition.Google Scholar
  12. 12.
    P. E. Dodd, F. W. Sexton, and P. S. Winokur, “Three-dimensional simulation of charge collection and multiple-bit upset in Si devices,” IEEE Transactions on Nuclear Science, vol. 41, pp. 2005–2017, 1994.CrossRefGoogle Scholar
  13. 13.
    P. E. Dodd, “Device simulation of charge collection and single-event upset,” IEEE Transactions on Nuclear Science, vol. 43, no. 2, pp. 561–575, Apr. 1996.Google Scholar
  14. 14.
    P. E. Dodd and L. W. Massengill, “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 583– 602, 2003.CrossRefGoogle Scholar
  15. 15.
    J. M. Palau, M. C. Calvet, P. E. Dodd, F. W. Sexton, and P. Roche, “Contribution of device simulation to SER understanding,” in Proc. of the Intl. Reliability Physics Symposium, March 2003, pp. 71–75.Google Scholar
  16. 16.
    P. Hazucha, C. Svensson, and S. A. Wender, “Cosmic-ray soft error rate characterization of a standard 0.6-μm CMOS process,” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1422–1429, Oct 2000.CrossRefGoogle Scholar
  17. 17.
    P. E. Dodd, M. R. Shaneyfelt, and F. W. Sexton, “Charge collection and SEU from angled ion strikes,” IEEE Transactions on Nuclear Science, vol. 44, pp. 2256–2265, 1997.CrossRefGoogle Scholar
  18. 18.
    F. Irom, F. F. Farmanesh, A. H. Johnston, G. M. Swift, and D. G. Millward, “Single-event upset in commercial silicon-on-insulator PowerPC microprocessors,” IEEE Transactions on Nuclear Science, vol. 49, no. 6, pp. 3148–3155, Dec 2002.CrossRefGoogle Scholar
  19. 19.
    O. Flament, J. Baggio, C. D’hose, G. Gasiot, and J. L. Leray, “14 MeV neutron-induced SEU in SRAM devices,” IEEE Transactions on Nuclear Science, vol. 51, no. 5, pp. 2908–2911, Oct. 2004.Google Scholar
  20. 20.
    Nanoscale integration and modeling (NIMO) group (2007), ASU Predictive Technology Model [On-line], Available: http://www.eas.asu.edu/~ptm
  21. 21.
    P. E. Dodd, M. R. Shaneyfelt, J. A. Felix, and J. R. Schwank, “Production and propagation of single-event transients in high-speed digital logic ICs,” IEEE Transactions on Nuclear Science, vol. 51, no. 6, pp. 3278–3284, Dec. 2004.Google Scholar
  22. 22.
    O. A. Amusan, “Analysis of single event vulnerabilities in a 130 nm CMOS technology,” M.S. thesis, Vanderbilt University, 2006.Google Scholar
  23. 23.
    S. DasGupta, “Trends in single event pulse widths and pulse shapes in deep submicron CMOS,” M.S. thesis, Vanderbilt University, 2008.Google Scholar
  24. 24.
    P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, and V. Chikarmane et al., “A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57μm 2 SRAM cell,” International Electron Devices Meeting, pp. 657–660, Dec. 2004.Google Scholar
  25. 25.
    S. Chen, H. Huang, H. Lin, L. Shie, and M. Chen, “Using simulation for characterize high performance 65nm node planar N-MOSFETs,” in Proc. of the Intl. Symposium on NANO Science and Technology, Nov. 2004, pp. 1–2.Google Scholar
  26. 26.
    Y. Taur and E. J. Nowak, “CMOS devices below 0.1 um: How high will performance go?,” International Electron Devices Meeting, pp. 215–218, Dec. 1997.Google Scholar
  27. 27.
    T. Fukai, Y. Nakahara, M. Terai, S. Koyama, and Y. Morikuni et al., “A 65 nm-node CMOS technology with highly reliable triple gate oxide suitable for power-considered system-on-a-chip,” Proc. of the Symposium on VLSI Technology, pp. 83–84, June 2003.Google Scholar
  28. 28.
    R. Baumann, “Soft errors in advanced computer systems,” IEEE Design & Test of Computers, vol. 22, no. 3, pp. 258–266, May-June 2005.Google Scholar

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© Springer-Verlag US 2010

Authors and Affiliations

  1. 1.HillsboroUSA
  2. 2.Department of Electrical and Computer EngineeringTexas A & M UniversityCollege StationUSA

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