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Power-Aware Testing and Test Strategies for Low Power Devices pp 213–242Cite as

Low-Power Design Techniques and Test Implications

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Abstract

This chapter provides a brief overview of the prevalent design techniques for dynamic and leakage power reduction in both logic and memory circuits. It also provides an introduction to power specification format, which allows specification of circuit properties with respect to power dissipation in a consistent manner. Next, it discusses the impact of existing low-power design techniques on test. Finally, it covers the test implications of the post-silicon adaptation approaches for power reduction.

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Acknowledgements

We would like to express our appreciation to Dr. Swaroop Ghosh, Prof. Chris Kim, Mr. Seetharam Narasimhan, and Mr. Rajat Subhra Chakraborty for providing important help with the technical content and presentation of the chapter.

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Authors and Affiliations

  1. Purdue University, West Lafayette, IN, USA

    Kaushik Roy

  2. Case Western Reserve University, Cleveland, OH, USA

    Swarup Bhunia

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  1. Kaushik Roy
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  2. Swarup Bhunia
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Correspondence to Kaushik Roy .

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Editors and Affiliations

  1. de Robotique de Microélectronique de, LIRMM - Laboratoire d'Informatique, Rue Ada 161, Montpellier, 34392, France

    Patrick Girard

  2. Dept. Electrical &, McMaster University, Main Street West 1280, Hamilton, L8S 4K1, Canada

    Nicola Nicolici

  3. Dept. Computer Science & Electronics, Kyushu Institute of Technology, Kawazu 680-4, Iizuka, 820-8502, Japan

    Xiaoqing Wen

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Roy, K., Bhunia, S. (2010). Low-Power Design Techniques and Test Implications. In: Girard, P., Nicolici, N., Wen, X. (eds) Power-Aware Testing and Test Strategies for Low Power Devices. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0928-2_7

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  • DOI: https://doi.org/10.1007/978-1-4419-0928-2_7

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