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Power-Aware System-Level Test Planning

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Power-Aware Testing and Test Strategies for Low Power Devices

Abstract

The high test power consumption, which can be several factors higher than the functional power consumption for which an integrated circuit (IC) is designed, may result in higher overall cost due to yield loss and potentially damaged ICs. As system-on-chips (SOCs) designed in modular fashion are becoming increasingly common, the testing can, in contrast to nonmodular SOCs, be performed in a modular manner. The key advantage is that modular test offers the possibility to plan the testing such that power consumption is controlled; modules are only activated when they are tested. This chapter contains an introduction to core-based testing, which is followed by a discussion on test power consumption and its modeling, and then the chapter discusses power-aware test planning for modular SOCs.

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Authors and Affiliations

  1. Linköping University, Linköping, Sweden

    Erik Larsson

  2. Texas Instruments Inc., Bangalore, India

    C. P. Ravikumar

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  1. Erik Larsson
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Correspondence to Erik Larsson .

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Editors and Affiliations

  1. de Robotique de Microélectronique de, LIRMM - Laboratoire d'Informatique, Rue Ada 161, Montpellier, 34392, France

    Patrick Girard

  2. Dept. Electrical &, McMaster University, Main Street West 1280, Hamilton, L8S 4K1, Canada

    Nicola Nicolici

  3. Dept. Computer Science & Electronics, Kyushu Institute of Technology, Kawazu 680-4, Iizuka, 820-8502, Japan

    Xiaoqing Wen

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Larsson, E., Ravikumar, C.P. (2010). Power-Aware System-Level Test Planning. In: Girard, P., Nicolici, N., Wen, X. (eds) Power-Aware Testing and Test Strategies for Low Power Devices. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0928-2_6

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