EDA Solution for Power-Aware Design-for-Test



Previous chapters of this book covered various techniques for testing low-power devices. The objective of this chapter is to help design-for-test experts understand challenges related to implementing these techniques in EDA flows. EDA tools have been constantly challenged with problems related to integrating DFT insertion with logical/physical synthesis and timing closure. Power gating techniques add power as a significant dimension to the complexity. DFT insertion tools must be made power-aware so that DFT logic such as scan can be correctly architected across different power domains and voltage islands. At the same time, any DFT inserted logic must have the minimum possible impact on power consumption. The user has, now more than ever, to be well prepared to make trade-off decisions as each technique brings its new set of constraints and implementation costs. In this chapter, we describe the challenges facing the EDA industry, discuss some existing solutions, and finally, we propose some future directions.


Power Dissipation Test Mode Power Mode Level Shifter Design Flow 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The author wishes to thank James D. Sproch, Senior Director of Research and Development at Synopsys and recognized expert on low-power design and test issues, for his valuable input and detailed review of this chapter; Prof. Xiaoqing Wen of Kyushu Institute of Technology, Japan, Prof. Nicola Nicolici of McMaster University, Canada and Prof. Patrick Girard of LIRMM, France, for their effort and patience in putting together the book and their review of the manuscript.


  1. Beausang J, Ellingham C, Robinson M (1996) Integrating scan into hierarchical synthesis methodologies. Proc IEEE Int Test Conf (ITC 1996), 751–756Google Scholar
  2. Brophy D (2008) IEEE P1801 – The unified power format for low power designs. UPF Tutorial at Design Automation and Test in Europe (DATE), http://www.accellera.org/activities/p1801_upf/DATE-UPF-Final_2008.pdf
  3. Chakravadhanula K, Chikermane V, Keller B,Gallagher P, Gregor S (2008) Test generation for state retention logic. Proc IEEE 17th Asian Test Symp (ATS 2008), 237–242Google Scholar
  4. Chickermane V, Gallagher P, Sage J, Yuan P, Chakravadhanula K (2008) A power-aware test methodology for multi-supply multi-voltage designs. Proc IEEE Int Test Conf (ITC 2008), Paper 9.1Google Scholar
  5. CPF (2007) Si2 common power format specifications, http://www.si2.org/, 2007
  6. CTL (2006) IEEE 1450.6 standard test interface language (STIL) for digital test vector data – core test language (CTL), IEEE Computer Society, April 2006Google Scholar
  7. Czysz D, Kassab M, Lin X, Mrugalski G, Rajski J, Tyszer J (2008) Low power scan shift and capture in the EDT environment. Proc IEEE Int Test Conf (ITC 2008), Paper 13.2, 1–10Google Scholar
  8. De Colle A, Ramnath S, Hirech M, Chebiyam S (2005) Power and design for test: a design automation perspective. J Low Power Electronics (JOLPE) 1(1):73–84CrossRefGoogle Scholar
  9. DevanathanVR, Ravikumar CP, Mehrotra R, Kamakoti V (2007) PMScan: a power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. Proc IEEE Test Int Conf (ITC 2007), Paper 13.3, 1–9Google Scholar
  10. DFTMAX (2008) DFT Compiler/DFTMAX User Guide, version B-2008.09Google Scholar
  11. ElShoukry M, Tahranipoor M, Ravikumar CP (2005) Partial gating optimization for power reduction during test application. Proc IEEE 14th Asian Test Symp (ATS 2005), 242–247.Google Scholar
  12. Gerstendorfer S, Wunderlich H-J (1999) Minimized power consumption for scan-based BIST. Proc IEEE Int Test Conf (ITC 1999), 77–84Google Scholar
  13. Goel SK, Meijer M, de Gyvez JP (2006) Testing and diagnosis of power switches in SOCs. Proc IEEE 11th Eur Test Symp (ETS 2006), 145–150Google Scholar
  14. Goering R (2008) Automating low power design – a progress report. SCD source, issue 1, http://www.scdsource.com/download.php?=SCDsource_STR_LowPower.pdf
  15. Hattori T, Irita T, Ito M, Kato H, Sado G, Yamada Y, Nishiyama K, Yagi H, Koike T, Tsuchihashi Y, Higashida M, Asano H, Hayashibara I, Tatezawa K, Shimazaki Y, Morino N, Hirose K, Tamaki S, Yoshioka S, Tsuchihashi R, Arai N, Akiyama T, Ohno K (2006a) A power management scheme controlling 20 power domains for a single-chip mobile processor. Digest Tech Papers IEEE Int Solid-State Circuits Conf (ISSCC 2006), Paper 29.5, 2210–2219Google Scholar
  16. Hattori T, Irita T, Ito M, Yamamoto E, Kato H, Yamada T, Nishiyama K, Yagi H, Koike T, Tsuchihashi Y, Higashida M, Asano H, Hayashibara I, Tatezawa K, Shimazaki S, Morino N, Yasu Y, Hoshi T, Miyairi Y, Yanagisawa K, Hirose K, Tamaki S, Yoshioka S, Ishii T, Kanno Y, Mizuno H, Yamada Y, Irie N, Tsuchihashi R, Arai N, Akiyama T, Ohno K (2006b) Hierarchical power distribution and power management scheme for a single chip mobile processor. Proc IEEE Design Automation Conf (DAC 2006), 292–295Google Scholar
  17. Idgunji S (2007) Case study of a low power MTCMOS based ARM926 SoC: design, analysis and test challenges. Proc IEEE Int Test Conf (ITC 2007), Lecture 2.3, 1–10Google Scholar
  18. Keating M, Flynn D, Aitken R, Gibbons A, Shi K (2007) Low power methodology manual: for system-on-chip design. Springer, New York, Edition 2007Google Scholar
  19. Mrugalski G, Rajski J, Czysz D, Tyszer J (2007) New test data decompressor for low power applications. Proc IEEE Design Automation Conf (DAC 2007), 539–544Google Scholar
  20. Ramnath S, Neuveux F, Hirech M, Ng F (2002) Test-model based hierarchical DFT synthesis. Proc IEEE Int Conf Comput Aided Design (ICCAD 2002), 286–293Google Scholar
  21. Ravi S (2007) Power-aware test: challenges and solutions. Proc IEEE Int Test Conf (ITC 2007), Lecture 2.2, 1–10Google Scholar
  22. Ravikumar CP, Hirech M, Wen X (2008) Test strategies for low power devices. Proc IEEE Design Automation Test Eur (DATE 2008), 728–733Google Scholar
  23. Souef L, Eychenne C, Alie E (2008) Architecture for testing multi-voltage domain SOC. Proc IEEE Int Test Conf (ITC 2008), Paper 16.1, 1–10Google Scholar
  24. Std-1801 (2009) 1801 – IEEE standard for design and verification of low power integrated circuits. IEEE Computer Society, March 2009Google Scholar
  25. Synopsys (2007) Synopsys low-power solution. White paper, June 2007, http://www.synopsys.com/lowpower/wp/lp_solution_wp.pdf
  26. TetraMAX (2008) TetraMAX ATPG User Guide, version B-2008.09. Synopsys. Inc., Sept. 2008Google Scholar
  27. UPF (2007) Unified Power Format (UPF) Standard, Version 1.0, Feb. 22, 2007, http://www.accellera.org/apps/group_public/download.php/989/upf.v1.0.pdf
  28. Zyuban V, Kosonocky SV (2002) Low power integrated scan-retention mechanism. Proc IEEE Int Symp Low Power Electronics Design (ISLPED 2002), 98–102Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Synopsys Inc.Mountain ViewUSA

Personalised recommendations