Abstract
Previous chapters of this book covered various techniques for testing low-power devices. The objective of this chapter is to help design-for-test experts understand challenges related to implementing these techniques in EDA flows. EDA tools have been constantly challenged with problems related to integrating DFT insertion with logical/physical synthesis and timing closure. Power gating techniques add power as a significant dimension to the complexity. DFT insertion tools must be made power-aware so that DFT logic such as scan can be correctly architected across different power domains and voltage islands. At the same time, any DFT inserted logic must have the minimum possible impact on power consumption. The user has, now more than ever, to be well prepared to make trade-off decisions as each technique brings its new set of constraints and implementation costs. In this chapter, we describe the challenges facing the EDA industry, discuss some existing solutions, and finally, we propose some future directions.
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Acknowledgements
The author wishes to thank James D. Sproch, Senior Director of Research and Development at Synopsys and recognized expert on low-power design and test issues, for his valuable input and detailed review of this chapter; Prof. Xiaoqing Wen of Kyushu Institute of Technology, Japan, Prof. Nicola Nicolici of McMaster University, Canada and Prof. Patrick Girard of LIRMM, France, for their effort and patience in putting together the book and their review of the manuscript.
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Hirech, M. (2010). EDA Solution for Power-Aware Design-for-Test. In: Girard, P., Nicolici, N., Wen, X. (eds) Power-Aware Testing and Test Strategies for Low Power Devices. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0928-2_11
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