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PicoServer: Using 3D Stacking Technology to Build Energy Efficient Servers

  • Taeho Kgil
  • David Roberts
  • Trevor Mudge
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

With power and cooling increasingly contributing to the operating costs of a datacenter, energy efficiency is the key driver in server design. One way to improve energy efficiency is to implement innovative interconnect technologies such as 3D stacking. Three-dimensional stacking technology introduces new opportunities for future servers to become low power, compact, and possibly mobile. This chapter introduces an architecture called Picoserver that employs 3D technology to bond one die containing several simple slow processing cores with multiple memory dies sufficient for a primary memory. The multiple memory dies are composed of DRAM. This use of 3D stacks readily facilitates wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency means that thermal constraints, a concern with 3D stacking, are easily satisfied. PicoServer is intentionally simple, requiring only the simplest form of 3D technology where die are stacked on top of one another. Our intent is to minimize risk of introducing a new technology (3D) to implement a class of low-cost, low-power, compact server architectures.

Keywords

Access Latency Client Request NAND Flash Disk Cache Server Workload 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

This work is supported in part by the National Science Foundation, Intel, and ARM Ltd.

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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.IntelHillsboroUSA
  2. 2.University of MichiganAnn ArborUSA

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