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Thermal Via Insertion and Thermally Aware Routing in 3D ICs

  • Sachin S. Sapatnekar
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

Thermal challenges in 3D chips motivate the need for on-chip thermal conduction networks to deliver the heat to the heat sink. The most prominent example is a passive network of thermal vias, which serves the function of heat conduction without necessarily serving any electrical function. This chapter begins with an overview of techniques for thermal via insertion. Next, it addresses the problem of 3D routing, overcoming challenges as conventional 2D routing is stretched to a third dimension and as electrical routes must vie with thermal vias for scarce on-chip routing resources, particularly intertier vias.

Keywords

Heat Sink Sequential Quadratic Programming Thermal Problem Model Order Reduction Technique Lateral Overflow 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

Thanks to Brent Goplen and Tianpei Zhang, and the UCLA group led by Jason Cong, whose work has contributed significantly to the contents of this chapter.

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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringUniversity of MinnesotaMinneapolisUSA

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