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Thermal-Aware 3D Placement

  • Jason Cong
  • Guojie Luo
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

Three-dimensional IC technology enables an additional dimension of freedom for circuit design. Challenges arise for placement tools to handle the through-silicon via (TS via) resource and the thermal problem, in addition to the optimization of device layer assignment of cells for better wirelength. This chapter introduces several 3D global placement techniques to address these issues, including partitioning-based techniques, quadratic uniformity modeling techniques, multilevel placement techniques, and transformation-based techniques. The legalization and detailed placement problems for 3D IC designs are also briefly introduced. The effects of various 3D placement techniques on wirelength, TS via number, and temperature, and the impact of 3D IC technology to wirelength and repeater usage are demonstrated by experimental results.

Keywords

Placement Problem Device Layer Placement Technique Analytical Placement Layer Assignment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgment

This study was partially supported by the Gigascale Silicon Research Center, by IBM under a DARPA subcontract, and by the National Science Foundation under CCF-0430077 and CCF-0528583.

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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.UCLA Computer Science DepartmentCalifornia NanoSystems InstituteLos AngelesUSA
  2. 2.Department of Computer ScienceUniversity of CaliforniaLos AngelesUSA

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