Advertisement

Thermal and Power Delivery Challenges in 3D ICs

  • Pulkit Jain
  • Pingqiang Zhou
  • Chris H. Kim
  • Sachin S. Sapatnekar
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration per unit footprint. While this property is attractive for many applications, it also creates more stringent design bottlenecks in the areas of thermal management and power delivery. First, due to increased integration, the amount of heat per unit footprint increases, resulting in the potential for higher on-chip temperatures. The task of thermal management must necessarily be shared both by the heat sink, which transfers internally generated heat to the ambient, and by using thermally conscious design methods. Second, the power to be delivered to a 3D chip, per package pin, is tremendously increased, leading to significant complications in the task of reliable power delivery. This chapter presents an overview of both of these problems and outlines solution schemes to overcome the corresponding bottlenecks.

Keywords

Power Grid Finite Difference Method Power Delivery Negative Bias Temperature Instability Middle Tier 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
  2. 2.
    M. A. Alam, B. E. Weir, and P. J. Silverman. A study of soft and hard breakdown - part II: Principles of area, thickness, and voltage scaling. IEEE Transactions on Electron Devices, 49(2):239–246, February 2002.CrossRefGoogle Scholar
  3. 3.
    M. Armacost, A. Augustin, P. Felsner, Y. Feng, G. Friese, J. Heidenreich, G. Hueckel, O. Prigge, and K. Stein. A high reliability metal insulator metal capacitor for 0.18 μm copper technology. In Proceedings of the IEEE International Electronic Devices Meeting, pp. 157–160, 2000.Google Scholar
  4. 4.
    Semiconductor Industry Association. International technology roadmap for semiconductors (ITRS), 2007. http://public.itrs.net/.
  5. 5.
    J. A. Burns, B. F. Aull, C. K. Chen, C. L. Keast, J. M. Knecht, V. Suntharalingam, K. Warner, P. W. Wyatt, and D. Yost. A wafer-scale 3-D circuit integration technology. IEEE Transactions on Electron Devices, 53(10):2507–2516, October 2006.CrossRefGoogle Scholar
  6. 6.
    S. Chandrasekaran, J. Sun, and V. Mehrotra. Vertically packaged switched-mode power converter, 2006. US Patent #7012414.Google Scholar
  7. 7.
    L. O. Chua and P.-M. Lin. Computed-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques. Prentice-Hall, Englewood Cliffs, NJ, 1975.Google Scholar
  8. 8.
    C. M. Fiduccia and R. M. Mattheyses. A linear-time heuristic for improving network partitions. In Proceedings of the ACM/IEEE Design Automation Conference, pp. 175–181, 1982.Google Scholar
  9. 9.
    G. Golub and C. F. Van Loan. Matrix Computations. John Hopkins University Press, Baltimore, MD, 3rd edition, 1996.Google Scholar
  10. 10.
    B. Goplen. Advanced Placement Techniques for Future VLSI Circuits. PhD thesis, University of Minnesota, Minneapolis, MN, 2006.Google Scholar
  11. 11.
    B. Goplen and S. S. Sapatnekar. Efficient thermal placement of standard cells in 3D ICs using a force directed approach. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 86–89, 2003.Google Scholar
  12. 12.
    J. Gu, H. Eom, and C. H. Kim. Sleep transistor sizing and control for resonant supply noise damping. In Proceedings of the ACM International Symposium on Low Power Electronics and Design, pp. 80–85, 2007.Google Scholar
  13. 13.
    J. Gu, H. Eom, and C. H. Kim. A switched decoupling capacitor circuit for on-chip supply resonance damping. In Proceedings of the IEEE International Symposium on VLSI Circuits, pp. 126–127, 2007.Google Scholar
  14. 14.
    J. Gu and C. H. Kim. Multi-story power delivery for supply noise reduction and low voltage operation. In Proceedings of the ACM International Symposium on Low Power Electronics and Design, pp. 192–197, 2005.Google Scholar
  15. 15.
    E. Hailu, D. Boerstler, K. Miki, J. Qi, M. Wang, and M. Riley. A circuit for reducing large transient current effects on processor power grids. In Proceedings of the IEEE International Solid-State Circuits Conference, pp. 2238–2245, 2006.Google Scholar
  16. 16.
    J. A. Harrison and E. R. Stanford. Z-axis processor power delivery system, 2003. US Patent #6523253.Google Scholar
  17. 17.
    P. Hazucha, G. Schrom, J. Hahn, B. A. Bloechel, P. Hack, G. E. Dermer, S. Narendra, D. Gardner, T. Karnik, V. De, and S. Borkar. A 233-MHz 80%–87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE Journal of Solid-State Circuits, 40(4):838–845, April 2005.CrossRefGoogle Scholar
  18. 18.
    H. Hu, S.-J. Ding, H. F. Lim, C. Zhu, M. F. Li, S. J. Kim, X. F. Yu, J. H. Chen, Y. F. Yong, B. J. Cho, D.S.H. Chan, S. C. Rustagi, M. B. Yu, C. H. Tung, A. Du, D. My, P. D. Foot, A. Chin, and D.-L. Kwong. High performance ALD HfO2-Al2O3 laminate MIM capacitors for RF and mixed signal IC applications. In Proceedings of the IEEE International Electronic Devices Meeting, pp. 15.6.1–15.6.4, 2003.Google Scholar
  19. 19.
    G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. D. Meindl. Power delivery for 3D chip stacks: Physical modeling and design implication. In Proceedings of the IEEE Electrical Performance of Electronic Packaging Meeting, pp. 205–208, 2007.Google Scholar
  20. 20.
    P. Jain, T. Kim, J. Keane, and C. H. Kim. A multi-story power delivery technique for 3D integrated circuits. In Proceedings of the ACM International Symposium on Low Power Electronics and Design, pp. 57–62, 2008.Google Scholar
  21. 21.
    C. Keast, B. Aull, J. Burns, N. Checka, C.-L. Chen, C. Chen, M. Fritze, J. Kedzierski, J. Knecht, B. Tyrrell, K. Warner, B. Wheeler, D. Shaver, V. Suntharlingam, and D. Yost. 3D integration for integrated circuits and advanced focal planes, 2007. Available at http://vmsstreamer1.fnal.gov/VMS_Site_03/Lectures/Colloquium/070228Keast/index.htm .
  22. 22.
    K. H. Kim, J. Kim, H. J. Kim, S. H. Han, and H. J. Kim. A megahertz switching DC/DC converter using FeBN thin film inductor. IEEE Transactions on Magnetics, 38(5):3162–3164, September 2002.CrossRefMathSciNetGoogle Scholar
  23. 23.
    P. Li, L. T. Pileggi, M. Asheghi, and R. Chandra. Efficient full-chip thermal modeling and analysis. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 319–326, 2004.Google Scholar
  24. 24.
    P. Li, L. T. Pileggi, M. Asheghi, and R. Chandra. IC thermal simulation and modeling via efficient multigrid-based approaches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(9):1763–1776, September 2006.CrossRefGoogle Scholar
  25. 25.
    D. L. Logan. A First Course in the Finite Element Method. Brooks/Cole Publishing Company, Pacific Grove, CA, 3rd edition, 2002.Google Scholar
  26. 26.
    R. Mahajan, R. Nair, V. Wakharkar, J. Swan, J. Tang, and G. Vandentop. Emerging directions for packaging technologies. Intel Technology Journal, 6(2):62–75, May 2002.Google Scholar
  27. 27.
    J. R. Minz, S. K. Lim, and C.-K. Koh. 3D module placement for congestion and power noise reduction. In Proceedings of the Great Lakes Symposium on VLSI, pp. 458–461, 2005.Google Scholar
  28. 28.
    N. Na, T. Budell, C. Chiu, E. Tremble, and I. Wernple. The effects of on-chip and package decoupling capacitors and an efficient ASIC decoupling methodology. In Proceedings of the IEEE Electronic Components and Technology Conference, pp. 556–567, 2004.Google Scholar
  29. 29.
    M. N. Özişik. Heat Transfer: A Basic Approach. McGraw-Hill, New York, NY, 1985.Google Scholar
  30. 30.
    H. Qian, S. R. Nassif, and S. S. Sapatnekar. Random walks in a supply network. In Proceedings of the ACM/IEEE Design Automation Conference, pp. 93–98, 2003.Google Scholar
  31. 31.
    H. Qian and S. S. Sapatnekar. Hierarchical random-walk algorithms for power grid analysis. In Proceedings of the Asia-South Pacific Design Automation Conference, pp. 499–504, 2004.Google Scholar
  32. 32.
    S. Rajapandian, K. Shepard, P. Hazucha, and T. Karnik. High-tension power delivery: Operating 0.18 μm CMOS digital logic at 5.4 V. Proceedings of the IEEE International Solid-State Circuits Conference, pp. 298–599, February 2005.Google Scholar
  33. 33.
    V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan. Impact of negative bias temperature instability on digital circuit reliability. In Proceedings of the IEEE International Reliability Physics Symposium, pp. 248–254, 2002.Google Scholar
  34. 34.
    D. Roberts, W. Johnstone, H. Sanchez, O. Mandhana, D. Spilo, J. Hayden, E. Travis, B. Melnick, M. Celik, B. W. Min, J. Edgerton, M. Raymond, E. Luckowski, C. Happ, A. Martinez, B. Wilson, P. Leung, T. Garnett, D. Goedeke, T. Remmel, K. Ramakrishna, and B.E. Jr. White. Application of on-chip MIM decoupling capacitor for 90 nm SOI microprocessor. In Proceedings of the IEEE International Electronic Devices Meeting, pp. 72–75, 2005.Google Scholar
  35. 35.
    H. Sanchez, B. Johnstone, D. Roberts, O. Mandhana, B. Melnick, M.Celik, M. Baker, J. Hayden, B. Min, J. Edgerton, and B. White. Increasing microprocessor speed by massive application of on-die high-k MIM decoupling capacitors. In Proceedings of the IEEE International Solid-State Circuits Conference, pp. 2190–2199, 2006.Google Scholar
  36. 36.
    S. S. Sapatnekar and H. Su. Analysis and optimization of power grids. IEEE Design & Test, 20(3):7–15, 2003.CrossRefGoogle Scholar
  37. 37.
    G. Schrom, P. Hazucha, J. Hahn, V. Kursun, D. Gardner, S. Narendra, T. Karnik, and V. De. Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. In Proceedings of the ACM International Symposium on Low Power Electronics and Design, pp. 263–268, 2004.Google Scholar
  38. 38.
    K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayan, and D. Tarjan. Temperature-aware microarchitecture. In Proceedings of the ACM International Symposium on Computer Architecture, pp. 2–13, 2003.Google Scholar
  39. 39.
    J. Sun, J. Lu, D. Giuliano, T. P. Chow, and R. J. Gutmann. 3D power delivery for microprocessors and high-performance ASICs. In Proceedings of IEEE Applied Power Electronics Conference, pp. 127–133, 2007.Google Scholar
  40. 40.
    Y. L. Tu, H. L. Lin, L. L. Chao, D. Wu, C. S. Tsai, C. Wang, C. F. Huang, C. H. Lin, and J. Sun. Characterization and comparison of high-k metal-insulator-metal (MiM) capacitors in 0.13 μm cu BEOL for mixed-mode and RF applications. In Proceedings of the IEEE International Symposium on VLSI Circuits, pp. 79–80, 2003.Google Scholar
  41. 41.
    A. Waizman. CPU power supply impedance profile measurement using FFT and clock gating. In Proceedings of the IEEE Electrical Performance of Electronic Packaging Meeting, pp. 29–32, 2003.Google Scholar
  42. 42.
    J. Wibben and R. Harjani. A high efficiency DC-DC converter using 2 nH on-chip inductors. In Proceedings of the IEEE International Symposium on VLSI Circuits, pp. 22–23, 2007.Google Scholar
  43. 43.
    E. Wong, J. Minz, and S. K. Lim. Decoupling capacitor planning and sizing for noise and leakage reduction. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 395–400, 2006.Google Scholar
  44. 44.
    P. Wong, P. Xu, P. Yang, and F. C. Lee. Performance improvements of interleaving VRMs with coupling inductors. IEEE Transactions on Power Electronics, 16(4):499–507, July 2001.CrossRefGoogle Scholar
  45. 45.
    J. H. Wu. Through-Substrate Interconnects for 3-D Integration and RF Systems. PhD thesis, Department. of EECS, Massachusetts Institute of Technology, October 2006.Google Scholar
  46. 46.
    J. Xu, P. Hazucha, M. Huang, P. Aseron, F. Paillet, G. Schrom, J. Tschanz, and C. Zhao. On-die supply-resonance suppression using band-limited active damping. In Proceedings of the IEEE International Solid-State Circuits Conference, pp. 286–603, 2007.Google Scholar
  47. 47.
    Y. Zhan and S. S. Sapatnekar. Automated module assignment in stacked-Vdd designs for high-efficiency power delivery. ACM Journal on Emerging Technologies in Computing Systems, 4(4):1–20, 2008.CrossRefGoogle Scholar
  48. 48.
    Y. Zhan, T. Zhang, and S. S. Sapatnekar. Module assignment for pin-limited designs under the stacked-Vdd paradigm. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 656–659, 2007.Google Scholar
  49. 49.
    P. Zhou, K. Sridharan, and S. S. Sapatnekar. Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. In Proceedings of the Asia-South Pacific Design Automation Conference, pp. 179–184, 2009.Google Scholar
  50. 50.
    P. Zurcher, P. Alluri, P. Chu, A. Duvallet, C. Happ, R. Henderson, J. Mendonca, M. Kim, M. Petras, M. Raymond, T. Remmel, D. Roberts, B. Steimle, J. Stipanuk, S. Straub, T. Sparks, M. Tarabbia, H. Thibieroz, and M. Miller. Integration of thin film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologies. In Proceedings of the IEEE International Electronic Devices Meeting, pp. 153–156, 2000.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Pulkit Jain
    • 1
  • Pingqiang Zhou
    • 1
  • Chris H. Kim
    • 1
  • Sachin S. Sapatnekar
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of MinnesotaMinneapolisUSA

Personalised recommendations