3D Process Technology Considerations

  • Albert M. Young
  • Steven J. Koester
Part of the Integrated Circuits and Systems book series (ICIR)


Both form-factor and performance-scaling trends are driving the need for 3D integration, which is now seeing rapid commercialization. While overall process integration schemes are not yet standardized across the industry, it is now important for 3D circuit designers to understand the process trends and tradeoffs that underlie 3D technology. In this chapter, we outline the basic process considerations that designers need to be aware of: strata orientation, inter-strata alignment, bonding-interface design, TSV dimensions, and integration with CMOS processing. These considerations all have direct implications on design and will be important in both the selection of 3D processes and the optimization of circuits within a given 3D process.


Bonding Process Wafer Bonding Etch Stop Silicon Thickness Alignment Tolerance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The authors wish to thank the following people for their contributions to this work: Roy R. Yu, Sampath Purushothaman, Kuan-neng Chen, Douglas C. La Tulipe, Narender Rana, Leathen Shi, Matthew R. Wordeman, Edmund J. Sprogis, Fei Liu, Steven Steen, Cornelia Tsang, Paul Andry, David Frank, Jyotica Patel, James Vichiconti, Deborah Neumayer, Robert Trzcinski, Latha Ramakrishnan, James Tornello, Michael Lofaro, Gil Singco, John Ott, David DiMilia, William Price, and Jesus Acevedo. The authors also acknowledge the support of the IBM Microelectronics Research Laboratory, and Central Scientific Services, as well as the staff at EV Group and Suss MicroTec. This project was funded in part by DARPA under SPAWAR contract numbers N66001-00-C-8003 and N66001-04-C-8032.


  1. 1.
    G. Moore, Cramming more components onto integrated circuits, Electronics 38, 114–117 (1965).Google Scholar
  2. 2.
    R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, Design of ion-implanted MOSFETs with very small physical dimensions, IEEE Journal of Solid-State Circuits, SC-9, 256–268 (1974).CrossRefGoogle Scholar
  3. 3.
    A. W. Topol, D. C. La Tulipe, L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, Three-dimensional integrated circuits, IBM Journal of Research & Development, 504: 91–506 (2006).Google Scholar
  4. 4.
    C. Narayan, S. Purushothaman, F. Doany, and A. Deutsch, Thin film transfer process for low cost MCM-D fabrication, IEEE Transaction Transactions on Components, Packaging, and Manufacturing Technology, B18: 42–46 (1995).CrossRefGoogle Scholar
  5. 5.
    E. D. Perfecto, R. R. Shields, A. K. Malhotra, M. P. Jeanneret, D. C. McHerron, and G. A. Katopis, MCM-D/C packaging solution for IBM latest S/390 servers, IEEE Transaction on Advance Packaging, 23: 515–520 (2000).CrossRefGoogle Scholar
  6. 6.
    S. E. Steen, D. C. La Tulipe, A. Topol, D. J. Frank, K. Belote, and D. Posillico, Wafer scale 3D integration: overlay as the key to drive potential, Microelectronic Engineering, 84: 1412–1415 (2007).CrossRefGoogle Scholar
  7. 7.
    A. W. Topol, D. C. La Tulipe, L. Shi, S. M. Alam, A. M. Young, D. J. Frank, S. E. Steen, J. Vichiconti, D. Posillico, D. M. Canaperi, S. Medd, R. A. Conti, S. Goma, D. Dimilia, C. Wang, L. Deligianni, M. A. Cobb, K. Jenkins, A. Kumar, K. T. Kwietniak, M. Robson, G. W. Gibson, C. D’Emic, E. Nowak, R. Joshi, K. W. Guarini, and M. Ieong, Assembly technology for three dimensional integrated circuits, Proceedings of 22nd International VLSI Multilevel Interconnection Conference (VMIC), pp. 83–88, Fremont CA, October 4–6, (2005).Google Scholar
  8. 8.
    K.-N. Chen, C. S. Tan, A. Fan, and R. Reif, Morphology and bond strength of copper wafer bonding, Electrochemical and Solid-State Letters, 7: G14–G16 (2004).CrossRefGoogle Scholar
  9. 9.
    K.-N. Chen, C. K. Tsang, A. W. Topol, S. H. Lee, B. K. Furman, D. L. Rath, J.-Q. Lu, A. M. Young, S. Purushothaman, and W. Haensch, Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages, 23rd International VLSI Multilevel Interconnection (VMIC) Conference, Fremont CA, September 25–28, 2006, VMIC Catalog No 06 IMIC-050, pp. 195–202 (2006).Google Scholar
  10. 10.
    K.-N. Chen. S. H. Lee, P. S. Andry, C. K. Tsang, A. W. Topol, Y. M. Lin, J. Q.Lu, A. M. Young, M. Ieong, and W. Haensch, Structure design and process control for Cu bonded interconnects in 3D integrated circuits, IEDM Technical Digest, 20–22 (2006).Google Scholar
  11. 11.
    H. B. Pogge, et al., Bridging the chip/package process divide, Proceedings of AMC, 129–136 (2001).Google Scholar
  12. 12.
    R. Yu, Wafer level 3D integration, International VLSI Multilevel Interconnection (VMIC) Conference, Fremont CA, September 24–27, (2007).Google Scholar
  13. 13.
    A. W. Topol, D. C. La Tulipe, L. Shi, S. M. Alam, D. J. Frank, S. E. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D. DiMilia, T. M. Robson, E. Duch, M. Farinelli, C. Wang, R. A. Conti, D. M. Canaperi, L. Deligianni, A. Kumar, K. T. Kwietniak, C. D’Emic, J. Ott, A. M. Young, K. W. Guarini, and M. Ieong, Enabling SOI based assembly technology for three-dimensional (3D) integrated circuits (ICs), IEDM Technical Digest, 363–366 (2005).Google Scholar
  14. 14.
    P. Leduc, F. de Crécy, M. Fayolle, B. Charlet, T. Enot, M. Zussy, B. Jones, J.-C. Barbe, N. Kernevez, N. Sillon, S. Maitrejean, D. Louis, and G. Passemard, Challenges for 3D IC integration: bonding quality and thermal management, Proceedings of IEEE International Interconnect Technology Conference (IITC), pp. 210–212 (2007).Google Scholar
  15. 15.
    A. W. Topol, S. J. Koester, D. C. La Tulipe, and A. M. Young, 3D fabrication options for high performance CMOS technology, Wafer Level 3D ICs Process Technology, C. S. Tan, R. J. Gutmann, and L. R. Reif, Eds., Springer, New York; ISBN 978-0-387-76532-7 (2008).Google Scholar
  16. 16.
    K. W. Guarini, et al., Process technologies for three dimensional integration, Proceedings of the 6th Annual International Conference on Microelectronics and Interfaces,American Vacuum Society, pp. 212–214 (2005).Google Scholar
  17. 17.
    C. K. Tsang, P. S. Andry, E. J. Sprogis, C. S. Patel, B. C. Webb, D. G. Manzer, and J. U. Knickerbocker, CMOS-compatible through silicon vias for 3D process integration, Proceedings of Material Research Society, 970: 145–153 (2006).Google Scholar
  18. 18.
    P. S. Andry, C. Tsang, E. J. Sprogis, C. Patel, S. L. Wright, and B. C. Webb, A CMOS-compatible process for fabricating electrical through-vias in silicon, Proceedings of the 56th Electronic Components and Technology Conference, San Diego, CA, pp. 831–837 (2006).Google Scholar
  19. 19.
    C. S. Patel, C. K. Tsang, C. Schuster, F. E. Doany, H. Nyikal, C. W. Baks, R. Budd, L. P. Buchwalter, P. S. Andry, D. F. Canaperi, D. C. Edelstein, R. Horton, J. U. Knickerbocker, T. Krywanczyk, Y. H. Kwark, K. T. Kwietniak, J. H. Magerlein, J. Rosner, and E. J. Sprogis, Silicon carrier with deep through vias, fine pitch wiring and through cavity for parallel optical transceiver, Proceedings of the 55th Electronic Components and Technology Conference, pp. 1318–1324 (2005).Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.IBM Thomas J. Watson Research CenterYorktown HeightsUSA

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