System-Level 3D IC Cost Analysis and Design Exploration
The majority of the existing 3D IC research has focused on how to take advantage of the performance, power, smaller form-factor, and heterogeneous integration benefits offered by 3D integration. However, all such advantages will ultimately have to be translatee into cost savings when a design strategy has to be decided. Consequently, system-level cost analysis at the early design stage is imperative to help the decision making on whether 3D integration should be adopted. In this chapter, we discuss the design estimation method for 3D ICs at the early design stage. We also describe a cost analysis model to study the cost implication for 3D ICs and address cost-related problems for 3D IC design.
The authors would like to thank Dr. Larry Smith from SEMATECH, Dr. Mike Ignatowski from IBM, Dr. Sam Gu from Qualcomm, and Dr. Pol Marchal from IMEC for the valuable discussions and guidance on this research. This work was supported in part by NSF grants of CAREER 0643902 and CCF 0702617, a grant from Qualcomm, and an IBM Faculty Award.
- 2.http://www.opensparc.net/. 2008.
- 3.IC Cost Model, 2008 revision 0808a. In IC Knowledge LLC, 2008.Google Scholar
- 4.S. Alam, R. Jones, S. Pozder, and A. Jain. Die/wafer stacking with reciprocal design symmetry (rds) for mask reuse in three-dimensional (3D) integration technology. In International Symposium on Quality Electronic Devices, 2009.Google Scholar
- 5.H. B. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, Reading, MA, 1990.Google Scholar
- 6.K. Bernstein. New dimension in performance. EDA Forum, 3(2), 2006.Google Scholar
- 7.S. Borkar. 3D-Technology: a system perspective. In International 3D-System Integration Conference, 2008.Google Scholar
- 8.P. Chong and R. K. Brayton. Estimating and optimizing routing utilization in DSM design. In Workshop System-Level Interconnect Prediction, 1999.Google Scholar
- 12.X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In Design Automation Conference, 2008.Google Scholar
- 15.G. H. Loh, Y. Xie, and B. Black. Processor design in 3D die-stacking technologies. MICRO, 27(3):31–48, 2007.Google Scholar
- 16.S. C. Marc Tremblay. A third-generation 65 nm 16-core 32-thread plus 32-scout-thread CMT SPARC(R) Processor. In International Solid State Circuit Conference, pp. 82–83, 2008.Google Scholar
- 17.J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits. Prentice-Hall, Englewood Cliffs, NJ, 2003.Google Scholar
- 18.L. Smith, G. Smith, S. Hosali, and S. Arkalgud. 3D: it all comes down to cost. Proceedings of RTI Conference of 3D Architecture for Semiconductors and Packaging, 2007.Google Scholar
- 19.R. Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen. Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. In ICCAD, pp. 212–219, 2007.Google Scholar