Navigating the Gap Using Architecture and Process Technology Scaling

Abstract

The measurement and analysis of the FPGA to ASIC gap in Chapter 3 found that there is significant room for improvement in the area, performance and power consumption of FPGAs. Whether it is possible to close the gap between FPGAs and ASICs is an important open question. Our analysis in Chapter 3 (by necessity) focused on a single FPGA design but there are in fact a multitude of different FPGA designs that can be created by varying the logical architecture, process technology, circuit design and transistor-level sizing of the device. The different designs within that rich design space offer trade-offs between area and performance but exploring these trade-offs is challenging because accuracy necessitates that each design be implemented down to the transistor-level. The automated transistor sizing tool described in the previous chapter makes such exploration feasible and this chapter will explore the impact of logical architecture and process technology on the area and performance of FPGAs. The following chapter will expand on this investigation by adding the dimensions of circuit design and transistor sizing to the conventional architectural changes considered in this chapter.