Measuring the Gap
The goal of this research is to explore the area, performance and power consumption gap between FPGAs and standard cell ASICs. The first step in this process is measuring the FPGA to ASIC gap. In the previous chapter, we described how all prior published attempts to make this comparison were superficial since none of those works focused exclusively on measuring this gap. In this chapter, we present a detailed methodology used to measure this gap and the resulting measurements. A key contribution is the analysis of the impact of logic block architecture, specifically the use of heterogeneous hard logic blocks, on the area, performance and power gap. These quantitative measurements of the FPGA to ASIC gap will benefit both FPGA architects, who aim to narrow the gap, and system designers, who select implementation media based on their knowledge of the gap. As well, this measurement of the gap motivates the latter half of the work in this book which explores the trade-offs that can be made to selectively narrow one dimension of the gap at the expense of another.
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