One goal of this book is to measure and understand the FPGA to ASIC gap. The gap is affected by many aspects of FPGA design including the FPGA’s architecture, the circuit structures used to implement the architectural features, and the sizing of the transistors within those circuits. In this chapter, the terminology and the conventional design approaches for these three areas are summarized. As well, the standard methodology for assessing the quality of an FPGA is reviewed. Such accurate assessments require the complete transistor-level design of the FPGA. However, transistor-level design is an arduous task and prior approaches to automated transistor sizing will be reviewed in this chapter. Finally, previous attempts at measuring the FPGA to ASIC gap are reviewed. This review will describe the issues that necessitated the more accurate comparison performed as part of this book.
KeywordsComplementary Metal Oxide Semiconductor Benchmark Circuit Switch Block FPGA Architecture Static Timing Analysis
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