Advertisement

Optimizing Memory Transactions for Multicore Systems

  • Ali-Reza Adl-Tabatabai
  • Christos Kozyrakis
  • Bratin Saha
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

The shift to multicore architectures will require new programming technologies that enable mainstream developers to write parallel programs that can safely take advantage of the parallelism offered by multicore processors. One challenging aspect of shared memory parallel programming is synchronization. Programmers have traditionally used locks for synchronization, but lock-based synchronization has well-known pitfalls that make it hard to use for building thread-safe and scalable software components. Memory transactions have emerged as a promising alternative to lock-based synchronization because they promise to eliminate many of the problems associated with locks. Transactional programming constructs, however, have overheads and require optimizations to make them practical. Transactions can also benefit significantly from hardware support, and multicore processors with their large transistor budgets and on-chip memory hierarchies have the opportunity to provide this support.

In this chapter, we discuss the design of transactional memory systems, focusing on software optimizations and hardware support to accelerate their performance. We show how programming languages, compilers, and language runtimes can support transactional memory. We describe optimization opportunities for reducing the overheads of transactional memory and show how the compiler and runtime can perform these optimizations. We describe a range of transactional memory hardware acceleration mechanisms spanning techniques that execute transactions completely in hardware to techniques that provide hardware acceleration for transactions executed mainly in software.

Keywords

Cache Line Multicore System Transactional Memory Multicore Processor Atomic Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    M. Abadi, A. Birrell, T. Harris, and M. Isard. Semantics of transactional memory and automatic mutual exclusion. In Proceedings of the Symposium on Principles of Programming Languages, San Francisco, CA, Jan 2008.Google Scholar
  2. 2.
    A.-R. Adl-Tabatabai, C. Kozyrakis, and B. Saha. Unlocking Concurrency. ACM Queue, 4:10, Dec 2006/Jan 2007.Google Scholar
  3. 3.
    A.-R. Adl-Tabatabai, B. T. Lewis, V. S. Menon, B. M. Murphy, B. Saha, and T. Shpeisman. Compiler and runtime support for efficient software transactional memory. In Proceedings of the Conference on Programming Language Design and Implementation, Ottawa, Canada, June 2006.Google Scholar
  4. 4.
    C. S. Ananian, K. Asanovic, B. C. Kuszmaul, C. E. Leiserson, and S. Lie. Unbounded transactional memory. In Proceedings of the 11th International Symposium on High-Performance Computer Architecture, Feb 2005.Google Scholar
  5. 5.
    B. Blanchet. Escape analysis for object-oriented languages: Application to Java. In Proceedings of the Conference on Object Oriented Programming Systems, Languages, and Architectures, 1999.Google Scholar
  6. 6.
    B. Bloom. Space/Time Trade-Offs in Hash Coding with Allowable Errors. Communications of ACM, 13(7), July 1970.Google Scholar
  7. 7.
    C. Blundell, E. C. Lewis, and M. M. K. Martin. Deconstructing transactions: The subtleties of atomicity. In Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking, 2005.Google Scholar
  8. 8.
    C. Cao Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford Transactional Applications for Multiprocessing. In Proceedings of the IEEE International Symposium on Workload Characterization, Seattle, WA, October 2008.Google Scholar
  9. 9.
    C. Cao Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An effective hybrid transactional memory system with strong isolation guarantees. In Proceedings of the International Symposium on Computer Architecture, San Diego, CA, June 2007.Google Scholar
  10. 10.
    B.D. Carlstrom, A. McDonald, H. Chafi, J.W. Chung, C.C Minh, C. Kozyrakis, and K. Olukotun. The ATOMO transactional programming language. In Proceedings of the Conference on Programming Language Design and Implementation, Ottawa, Canada, June 2006.Google Scholar
  11. 11.
    W. Chuang, S. Narayanasamy, G. Venkatesh, J. Sampson, M. Van Biesbrouck, M. Pokam, O. Colavin, and B. Calder. Unbounded page-based transactional memory. In Proceedings of the 12th International Conference on Architecture Support for Programming Languages and Operating Systems, San Jose, CA, Oct 2006.Google Scholar
  12. 12.
    J. Chung. System Challenges and Opportunities for Transactional Memory. Ph.D. thesis, Stanford University, June 2008.Google Scholar
  13. 13.
    J. Chung, C. Cao Minh, A. McDonald, T. Skare, H. Chafi, B. Carlstrom, C. Kozyrakis, and K. Olukotun. Tradeoffs in transactional memory virtualization. In Proceedings of the 12th International Conference on Architecture Support for Programming Languages and Operating Systems, San Jose, CA, October 2006.Google Scholar
  14. 14.
    P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir, and D. Nussbaum. Hybrid transactional memory. In Proceedings of the 12th International Conference on Architecture Support for Programming Languages and Operating Systems, San Jose, CA, October 2006.Google Scholar
  15. 15.
    D. Dice, O. Shalev, and N. Shavit. Transactional locking II. In Proceedings of the 20th International Symposium on Distributed Computing, Stockholm, Sweden, September 2006.Google Scholar
  16. 16.
    L. Hammond, B. Carlstrom, V. Wong, B. Hertzberg, M. Chen, C. Kozyrakis, and K. Olukotun. Programming with transactional coherence and consistency (TCC). In Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, Boston, MA, October 2004.Google Scholar
  17. 17.
    L. Hammond, V. Wong, M. Chen, B. Hertzberg, B. Carlstrom, M. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional memory coherence and consistency. In Proceedings of the 31st Annual International Symposium on Computer Architecture, Munich, Germany, June 2004.Google Scholar
  18. 18.
    T. Harris and K. Fraser. Language support for lightweight transactions. In Proceedings of the Conference on Object Oriented Programming Systems, Languages, and Architectures, Anaheim, CA, October 2003.Google Scholar
  19. 19.
    T. Harris, S. Marlow, S. P. Jones, and M. Herlihy. Composable memory transactions. In Proceedings of the Symposium on Principles and Practice of Parallel Programming, Chicago, IL, June 2005.Google Scholar
  20. 20.
    T. Harris, M. Plesko, A. Shinnar, and D. Tarditi. Optimizing memory transactions. In Proceedings of the Conference on Programming Languages Design and Implementation, Ottawa, Canada, June 2006.Google Scholar
  21. 21.
    M. Herlihy, V. Luchangco, M. Moir, and W. Scherer. Software transactional memory for dynamic-sized data structures. In Proceedings of the Twenty-Second Annual ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing (PODC), July 2003.Google Scholar
  22. 22.
    M. Herlihy and E. Moss. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, CA, May 2003.Google Scholar
  23. 23.
    R. L. Hudson, B. Saha, A.-R. Adl-Tabatabai, B. C. Hertzberg. McRT-Malloc: A scalable transactional memory allocator. In Proceedings of the International Symposium on Memory Management, Ottawa, Canada, June 2006.Google Scholar
  24. 24.
    S. Kumar, M. Chu, C. J. Hughes, P. Kundu, and A. Nguyen. Hybrid transactional memory. In Proceedings of the Symposium on Principles and Practices of Parallel Processing, Manhattan, New York, March, 2006.Google Scholar
  25. 25.
    A. McDonald, J. Chung, B. Carlstrom, C. Cao Minh, H. Chafi, C. Kozyrakis, and K. Olukotun. Architectural semantics for practical transactional memory. In Proceedings of the 33rd International Symposium on Computer Architecture, Boston, MA, June 2006.Google Scholar
  26. 26.
    V. Menon, S. Balensiefer, T. Shpeisman, A.-R. Adl-Tabatabai, R. L. Hudson, B. Saha, and A. Welc. Practical weak atomicity semantics for Java STM. In Proceedings of the Symposium on Parallelism in Algorithms and Architecture, Munich, Germany, June 2008.Google Scholar
  27. 27.
    K. Moore, J. Bobba, M. Moravan, M. Hill, and D. Wood. LogTM: Log-based transactional memory. In Proceedings of the 12th International Conference on High Performance Computer Architecture, Austin, TX, Feb 2006.Google Scholar
  28. 28.
    O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. Runahead execution: An alternative to very large instruction windows for out-of-order processors. In Proceedings of the 9th International Symposium on High-Performance Computer Architecture, Anaheim, CA, Feb 2003.Google Scholar
  29. 29.
    Y. Ni, A. Welc, A.-R. Adl-Tabatabai, M. Bach, S. Berkowits, J. Cownie, R. Geva, S. Kozhukow, R. Narayanaswamy, J. Olivier, S. Preis, B. Saha A. Tal, X. Tian. Design and implementation of transactional constructs for C/C++. In Proceedings of the Conference on Object Oriented Programming Systems, Languages, and Architectures, Nashville, TN, Oct 2008.Google Scholar
  30. 30.
    R. Rajwar and J. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In Proceedings of the 34th International Symposium on Microarchitecture, Istanbul, Turkey, Nov 2002.Google Scholar
  31. 31.
    R. Rajwar, M. Herlihy, and K. Lai. Virtualizing transactional memory. In Proceedings of the 32nd International Symposium on Computer Architecture, Madison, WI, June 2005.Google Scholar
  32. 32.
    B. Saha, A.-R. Adl-Tabatabai, R. Hudson, C. C. Minh, B. Hertzberg. McRT-STM: A high performance software transactional memory system for a multi-core runtime. In Proceedings of the Symposium on Principles and Practice of Parallel Programming, New York, Mar 2006.Google Scholar
  33. 33.
    B. Saha, A.-R. Adl-Tabatabai, and Q. Jacobson. Architectural support for software transactional memory. In Proceedings of the 39th International Symposium on Microarchitecture, Orlando, FL, Dec 2006.Google Scholar
  34. 34.
    W. N. Scherer III and M. L. Scott. Advanced contention management for dynamic software transactional memory. In Proceedings of the Symposium on Principles of Distributed Computing, Las Vegas, USA, July 2005.Google Scholar
  35. 35.
    F. Schneider, V. Menon, T. Shpeisman, and A.-R Adl-Tabatabai. Dynamic optimization for efficient strong atomicity. In Proceedings of the Conference on Object Oriented Programming Systems, Languages, and Architectures, Nashville, TN, Oct 2008.Google Scholar
  36. 36.
    T. Shpeisman, V. S. Menon, A.-R. Adl-Tabatabai, S. Balensiefer, D. Grossman, R. L. Hudson, K. Moore, and B. Saha. Enforcing isolation and ordering in STM. In Proceedings of the Conference on Programming Language Design and Implementation, San Diego, USA, June 2007.Google Scholar
  37. 37.
    A. Shriraman, M. Spear, H. Hossain, V. Marathe, S. Dwarkadas, and M. Scott. An integrated hardware–software approach to flexible transactional memory. In Proceedings of the 34th International Symposium on Computer Architecture, San Diego, CA, June 2007.Google Scholar
  38. 38.
    M. Spear, M. Michael, and M. Scott. Inevitability Mechanisms for Software Transactional Memory. Presented at the Workshop on Transactional Computing, Salt Lake City, UT, Feb 2008.Google Scholar
  39. 39.
    C. von Praun, L. Ceze, and C. Cascaval. Implicit parallelism with ordered transactions. In Proceedings of the Symposium on Principles and Practice of Parallel Programming, San Jose, CA, Mar 2007.Google Scholar
  40. 40.
    C. Wang, W. Chen, Y. Wu, B. Saha, and A.-R. Adl-Tabatabai. Code generation and optimization for transactional memory constructs in an unmanaged language. In Proceedings of the International Symposium on Code Generation and Optimization, San Jose, USA, Mar 2007.Google Scholar
  41. 41.
    A. Welc, B. Saha, and A.-R. Adl-Tabatabai. Irrevocable transactions and their applications. In Proceedings of the Symposium on Parallelism in Algorithms and Architectur e, Munich, Germany, June 2008.Google Scholar

Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  • Ali-Reza Adl-Tabatabai
    • 1
  • Christos Kozyrakis
    • 2
  • Bratin Saha
    • 1
  1. 1.Intel CorporationHillsboroUSA
  2. 2.Stanford UniversityStanfordUSA

Personalised recommendations