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Optimizing Memory Transactions for Multicore Systems

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Multicore Processors and Systems

Part of the book series: Integrated Circuits and Systems ((ICIR))

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Abstract

The shift to multicore architectures will require new programming technologies that enable mainstream developers to write parallel programs that can safely take advantage of the parallelism offered by multicore processors. One challenging aspect of shared memory parallel programming is synchronization. Programmers have traditionally used locks for synchronization, but lock-based synchronization has well-known pitfalls that make it hard to use for building thread-safe and scalable software components. Memory transactions have emerged as a promising alternative to lock-based synchronization because they promise to eliminate many of the problems associated with locks. Transactional programming constructs, however, have overheads and require optimizations to make them practical. Transactions can also benefit significantly from hardware support, and multicore processors with their large transistor budgets and on-chip memory hierarchies have the opportunity to provide this support.

In this chapter, we discuss the design of transactional memory systems, focusing on software optimizations and hardware support to accelerate their performance. We show how programming languages, compilers, and language runtimes can support transactional memory. We describe optimization opportunities for reducing the overheads of transactional memory and show how the compiler and runtime can perform these optimizations. We describe a range of transactional memory hardware acceleration mechanisms spanning techniques that execute transactions completely in hardware to techniques that provide hardware acceleration for transactions executed mainly in software.

“Unlocking Concurrency” [0] © [2006] ACM, Inc. Reprinted with permission.

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Author information

Authors and Affiliations

  1. Intel Corporation, Hillsboro, OR, USA

    Ali-Reza Adl-Tabatabai & Bratin Saha

  2. Stanford University, Stanford, CA, USA

    Christos Kozyrakis

Authors
  1. Ali-Reza Adl-Tabatabai
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  2. Christos Kozyrakis
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  3. Bratin Saha
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Corresponding author

Correspondence to Ali-Reza Adl-Tabatabai .

Editor information

Editors and Affiliations

  1. College of Natural Sciences, University of Texas, Austin, University Station 1, Austin, 78712-0233, U.S.A.

    Stephen W. Keckler

  2. Dept. Electrical Engineering, Stanford University, Stanford, 94305-9510, U.S.A.

    Kunle Olukotun

  3. IBM Software Group, Burnet Rd. 11501, Austin, 78758, U.S.A.

    H. Peter Hofstee

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© 2009 Springer-Verlag US

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Adl-Tabatabai, AR., Kozyrakis, C., Saha, B. (2009). Optimizing Memory Transactions for Multicore Systems. In: Keckler, S., Olukotun, K., Hofstee, H. (eds) Multicore Processors and Systems. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0263-4_5

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  • DOI: https://doi.org/10.1007/978-1-4419-0263-4_5

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  • Publisher Name: Springer, Boston, MA

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  • Online ISBN: 978-1-4419-0263-4

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