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Physical Design Considerations

  • Georgios Konstadinidis
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

Optimization of the structural skew alone, through balanced H or grid clock design and load balancing, is not adequate. Process, voltage, and temperature (PVT) variations dominate in most cases the total clock skew.While active deskew circuits [1–8] (also thoroughly described in Chaps.2 and 7, and the use of asynchronous FIFOs in clock domain crossings [9] can reduce the effect of skew, we still need to reduce the variation in the clock network to minimize the overall complexity and design effort. Higher skew would require larger number and extended range in the deskewing circuits. Increased clock skew would mean larger hold time violations that would require additional delay elements inserted in the critical path. This will increase area and power. This chapter focuses on physical design considerations to help minimize overall skew and to avoid overdesign. At first, we provide an overview of various skew components and explain their dependency on the process, voltage, and temperature variations. We describe the main sources of transistor variation including lithographic, layout, proximity, and strain related effects. Similarly, interconnects suffer from lithographic, process, and pattern density effects that add to the variability. We provide recommendations on how to optimize the layout to minimize both the transistor and interconnect variations, and provide answers to fundamental clock designer questions: How should I calculate the total process variation along a chain of clock buffers? Should I just add the variations of the individual stages or should I use a Root Mean Square approach? (It turns out none of the above approaches is correct if used in isolation.) What is the best approach in dealing with the voltage variation? Do all clock buffers see the same voltage variation? How does the temperature variation affect clock skew, and are there ways to compensate for this? What is the impact of inductance? Good understanding of the behavior of correlated vs. noncorrelated parameters will help us define the correct methodology for the delay variation estimation using well-established statistical techniques.

Keywords

Chemical Mechanical Polishing Path Delay Negative Bias Temperature Instability Clock Tree Clock Distribution 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    S. Tam, S. Rusu, U. Nagarji Desai, R. Kim, J. Zhang, and I. Young, “Clock generation and distribution for the first IA-64 microprocessor,” IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1545–1552, Nov. 2000.Google Scholar
  2. 2.
    T. Xanthopoulos, D. W. Bailey, A. K. Gangwar, M. K. Gowan, A. K. Jain, and B. K. Prewitt, “The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2001), 2001, pp. 402–403.Google Scholar
  3. 3.
    P. J. Restle, T. G. McNamara, D. A. Webber, P. J. Camporese, K. F. Eng, K. A. Jenkins, D. H. Allen, M. J. Rohn, M. P. Quaranta, D. W. Boerstler, C. J. Alpert, C. A. Carter, R. N. Bailey, J. G. Petrovick, B. L. Krauter, and B. D. McCredie, “A clock distribution network for microprocessors,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 792–799, May 2001.CrossRefGoogle Scholar
  4. 4.
    P. J. Restle, C. A. Carter, J. P. Eckhardt, B. L. Krauter, B. D. McCredie, K. A. Jenkins, A. J. Weger, and A. V. Mule, “The clock distribution of the Power4 microprocessor,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2002), vol. 1, 2002, pp. 144–145.Google Scholar
  5. 5.
    N. Bindal, T. Kelly, N. Velastegui, and K. L. Wong, “Scalable sub-10ps skew global clock distribution for a 90nm multi-GHz IA microprocessor,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2003), 2003, pp. 346–347,498.Google Scholar
  6. 6.
    S. Tam, R. D. Limaye, and U. N. Desai, “Clock generation and distribution for the 130-nm Itanium®; 2 processor with 6-MB on-die L3 cache,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 636–642, April 2004.CrossRefGoogle Scholar
  7. 7.
    P. Mahoney, E. Fetzer, B. Doyle, and S. Naffziger, “Clock distribution on a dual-core, multi-threaded Itanium®;-family processor,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2005), 2005, pp. 292–293,599.Google Scholar
  8. 8.
    M. G. R. Thomson, P. J. Restle, and N. K. James, “A 5 GHz duty-cycle correcting clock distribution network for the POWER6 microprocessor,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2006), 2006, pp. 1522–1529.Google Scholar
  9. 9.
    G. K. Konstadinidis, K. Normoyle, S. Wong, S. Bhutani, H. Stuimer, T. Johnson, A. Smith, D. Y. Cheung, F. Romano, S. Yu, S.-H. Oh, V. Melamed, S. Narayanan, D. Bunsey, C. Khieu, K. J. Wu, R. Schmitt, A. Dumlao, M. Sutera, J. Chau, K. J. Lin, and W. S. Coates, “Implementation of a third-generation 1.1-GHz 64-bit microprocessor,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1461–1469, Nov. 2002.Google Scholar
  10. 10.
    N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and System Perspective (third edition). Addison Wesley, Reading, MA, 2005.Google Scholar
  11. 11.
    A. Chandrakasan, W. Bowhill, and F. Fox, Design of High Performance Microprocessor Circuits. IEEE Press, 2001.Google Scholar
  12. 12.
    N. J. Rohrer, “Introduction to statistical variation and techniques for design optimization,” ISSCC 2006 Tutorial.Google Scholar
  13. 13.
    K. Ushida, “Future lithography challenges,” in Proceedings of the IEEE International Symposium on Semiconductor Manufacturing ISSM 2006, 25–27 Sept. 2006, pp. lv–lx.Google Scholar
  14. 14.
    S. Sivakumar, “Lithography challenges for 32 nm technologies and beyond,” in Proceedings of the International Electron Devices Meeting IEDM ’06, 11–13 Dec. 2006, pp. 1–4.Google Scholar
  15. 15.
    N. S. Nagaraj, T. Bonifield, A. Singh, R. Griesmer, and P. Balsara, “Interconnect modeling for copper/low-k technologies,” in Proceedings of the 17th International Conference on VLSI Design, 2004, pp. 425–427.Google Scholar
  16. 16.
    S. Tyagi, C. Auth, P. Bai, G. Curello, H. Deshpande, S. Gannavaram, O. Golonzka, R. Heussner, R. James, C. Kenyon, S. H. Lee, N. Lindert, M. Liu, R. Nagisetty, S. Natarajan, C. Parker, J. Sebastian, B. Sell, S. Sivakumar, A. S. Amour, and K. Tone, “An advanced low power, high performance, strained channel 65nm technology,” in Proceedings of the IEDM Technical Digest Electron Devices Meeting IEEE International, 5–7 Dec. 2005, pp. 245–247.Google Scholar
  17. 17.
    T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors,” in Proceedings of the IEDM ’03 Technical Digest Electron Devices Meeting IEEE International, 8–10 Dec. 2003, pp. 11.6.1–11.6.3.Google Scholar
  18. 18.
    S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, “A logic nanotechnology featuring strained-silicon,” IEEE Electron Device Lett., vol. 25, no. 4, pp. 191–193, April 2004.CrossRefGoogle Scholar
  19. 19.
    M. Horstmann, A. Wei, T. Kammler, J. Hntschel, H. Bierstedt, T. Feudel, K. Frohberg, M. Gerhardt, A. Hellmich, K. Hempel, J. Hohage, P. Javorka, J. Klais, G. Koerner, M. Lenski, A. Neu, R. Otterbach, P. Press, C. Reichel, M. Trentsch, B. Trui, H. Salz, M. Schaller, H. J. Engelmann, O. Herzog, H. Ruelke, P. Hubler, R. Stephan, D. Greenlaw, M. Raab, and N. Kepler, “Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies,” in Proceedings of IEDM Technical Digest Electron Devices Meeting IEEE International, 5–7 Dec. 2005, pp. 233–236.Google Scholar
  20. 20.
    P. Grudowski, V. Adams, X.-Z. Bo, K. Loiko, S. Filipiak, J. Hackenberg, M. Jahanbani, M. Azrak, S. Goktepeli, M. Shroff, W.-J. Liang, S. J. Lian, V. Kolagunta, N. Cave, C.-H. Wu, M. Foisy, H. C. Tuan, and J. Cheek, “1-D and 2-D geometry effects in uniaxially-strained dual etch stop layer stressor integrations,” in Proceedings of the Digest of Technical Papers VLSI Technology 2006 Symposium, 2006, pp. 62–63.Google Scholar
  21. 21.
    C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd, P. Stolk, F. Boeuf, and F. Arnaud, “Stress memorization technique (SMT) optimization for 45 nm CMOS,” in Proceedings of Digest of Technical Papers VLSI Technology 2006 Symposium, 2006, pp. 78–79.Google Scholar
  22. 22.
    M. Wiatr, T. Feudel, A. Wei, A. Mowry, R. Boschke, P. Javorka, A. Gehring, T. Kammler, M. Lenski, K. Frohberg, R. Richter, M. Horstmann, and D. Greenlaw, “Review on process-induced strain techniques for advanced logic technologies,” in Proceedings of the 15th International Conference on Advanced Thermal Processing of Semiconductors RTP 2007, 2–5 Oct. 2007, pp. 19–29.Google Scholar
  23. 23.
    V. Chan, R. Rengarajan, N. Rovedo, W. Jin, T. Hook, P. Nguyen, J. Chen, E. Nowak, X.-D. Chen, D. Lea, A. Chakravarti, V. Ku, S. Yang, A. Steegen, C. Baiocco, P. Shafer, H. Ng, S.-F. Huang, and C. Wann, “High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering,” in Proceedings of the IEDM ’03 Technical Digest Electron Devices Meeting IEEE International, 8–10 Dec. 2003, pp. 3.8.1–3.8.4.Google Scholar
  24. 24.
    C. Auth, A. Cappellani, J. S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, and C. Wiegand, “45nm high-k + metal gate strain-enhanced transistors,” in Proceedings of the Symposium on VLSI Technology, 17–19 June 2008, pp. 128–129.CrossRefGoogle Scholar
  25. 25.
    P. Ranade, T. Ghani, K. Kuhn, K. Mistry, S. Pae, L. Shifren, M. Stettler, K. Tone, S. Tyagi, and M. Bohr, “High performance 35nm LATE CMOS transistors featuring NiSi metal gate (FUSI), uniaxial strained silicon channels and 1.2 nm gate oxide,” in Proceedings of the IEDM Technical Digest Electron Devices Meeting IEEE International, 5–7 Dec. 2005, p. 4.Google Scholar
  26. 26.
    K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. Mclntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging,” in Proceedings of the IEEE International Electron Devices Meeting IEDM 2007, 10–12 Dec. 2007, pp. 247–250.Google Scholar
  27. 27.
    S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Yu, S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Warm, T. Ivers, and P. Agnello, “High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography,” in Proceedings of the International Electron Devices Meeting IEDM ’06, 11–13 Dec. 2006, pp. 1–4.Google Scholar
  28. 28.
    S. Suthram, Y. Sun, P. Majhi, I. Ok, H. Kim, H. R. Harris, N. Goel, S. Parthasarathy, A. Koehler, T. Acosta, T. Nishida, H.-H. Tseng, W. Tsai, J. Lee, R. Jammy, and S. E. Thompson, “Strain additivity in III-V channels for CMOSFETs beyond 22nm technology node,” in Proceedings of the Symposium on VLSI Technology, 17–19 June 2008, pp. 182–183.CrossRefGoogle Scholar
  29. 29.
    Y. M. Sheu, K. W. Su, S. Tian, S. J. Yang, C. C. Wang, M. J. Chen, and S. Liu, “Modeling the well-edge proximity effect in highly scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2792–2798, Nov. 2006.Google Scholar
  30. 30.
    I. Polishchuk, N. Mathur, C. Sandstrom, P. Manos, and O. Pohland, “CMOS Vt-control improvement through implant lateral scatter elimination,” in Proceedings of the IEEE International Symposium on Semiconductor Manufacturing ISSM 2005, 13–15 Sept. 2005, pp. 193–196.Google Scholar
  31. 31.
    P. G. Drennan, M. L. Kniffin, and D. R. Locascio, “Implications of proximity effects for analog design,” in Proceedings of the IEEE Custom Integrated Circuits Conference 2006, 10–13 Sept. 2006, pp. 169–176.Google Scholar
  32. 32.
    T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, and T. Watanabe, “Impact of well edge proximity effect on timing,” in Proceedings of the ESSCIRC 33rd European Solid State Circuits Conference, 11–13 Sept. 2007, pp. 115–118.Google Scholar
  33. 33.
    A. Asenov, S. Kaya, and A. R. Brown, “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness,” IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1254–1260, May 2003.CrossRefGoogle Scholar
  34. 34.
    A. Asenov, S. Kaya, and J. H. Davies, “Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations,” IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 112–119, Jan. 2002.Google Scholar
  35. 35.
    Y. Ye, F. Liu, S. Nassif, and Y. Cao, “Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness,” in Proceedings of the 45th ACM/IEEE Design Automation Conference DAC 2008, 8–13 June 2008, pp. 900–905.CrossRefGoogle Scholar
  36. 36.
    S. Borkar, “Designing reliable systems from unreliable components: the challenges of transistor variability and degradation,” IEEE Micro, vol. 25, no. 6, pp. 10–16, Nov.–Dec. 2005.Google Scholar
  37. 37.
    T. Karnik, V. De, and S. Borkar, “Statistical design for variation tolerance: key to continued Moore’s law,” in Proceedings of the International Conference on Integrated Circuit Design and Technology ICICDT ’04, 2004, pp. 175–176.Google Scholar
  38. 38.
    J. Rosal, “Multi-core SoC test and yield enhancement – Challenges and solutions,” ISSCC Microprocessor Forum, February 2006.Google Scholar
  39. 39.
    H. Masuda, S. Okawa, and M. Aoki, “Approach for physical design in sub-100 nm era,” in Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS 2005, 23–26 May 2005, pp. 5934–5937.Google Scholar
  40. 40.
    H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1787–1796, Sept. 2005.Google Scholar
  41. 41.
    A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies, and S. Saini, “Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-d density-gradient simulation study,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 722–729, April 2001.CrossRefGoogle Scholar
  42. 42.
    I. Ahsan, O. Glushchenkov, R. Logan, E. J. Nowak, H. Kimura, G. Berg, J. Herman, E. Maciejewski, A. Chan, A. Azuma, S. Deshpande, B. Dirahoui, G. Freeman, A. Gabor, M. Gribelyuk, S. Huang, M. Kumar, K. Miyamoto, D. Mocuta, A. Mahorowala, E. Leobandung, and H. Utomo, “RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology,” in Proceedings of the Digest of Technical Papers VLSI Technology 2006 Symposium, 2006, pp. 170–171.Google Scholar
  43. 43.
    T. Tanaka, T. Usuki, T. Futatsugi, Y. Momiyama, and T. Sugii, “v th fluctuation induced by statistical variation of pocket dopant profile,” in Proceedings of the IEDM Technical Digest Electron Devices Meeting International, 10–13 Dec. 2000, pp. 271–274.Google Scholar
  44. 44.
    D. S. Boning, K. Balakrishnan, H. Cai, N. Drego, A. Farahanchi, K. M. Gettings, L. Daihyun, A. Somani, H. Taylor, D. Truque, and X. Xiaolin, “Variation,” IEEE Trans. Semicond. Manuf., vol. 21, no. 1, pp. 63–71, Feb. 2008.Google Scholar
  45. 45.
    D. Harris and S. Naffziger, “Statistical clock skew modeling with data delay variations,” IEEE Trans. VLSI Syst., vol. 9, no. 6, pp. 888–898, Dec. 2001.Google Scholar
  46. 46.
    A. Agarwal, V. Zolotov, and D. T. Blaauw, “Statistical clock skew analysis considering intradie-process variations,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 8, pp. 1231–1242, Aug. 2004.Google Scholar
  47. 47.
    K. A. Bowman, S. G. Duvall, and J. D. Meindl, “Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration,” IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 183–190, Feb. 2002.Google Scholar
  48. 48.
    E. Malavasi, S. Zanella, M. Cao, J. Uschersohn, M. Misheloff, and C. Guardiani, “Impact analysis of process variability on clock skew,” in Proceedings of International Symposium on Quality Electronic Design, 18–21 March 2002, pp. 129–132.CrossRefGoogle Scholar
  49. 49.
    J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah, “Statistical timing for parametric yield prediction of digital integrated circuits,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 11, pp. 2376–2392, Nov. 2006.Google Scholar
  50. 50.
    Y. Zhan, A. J. Strojwas, X. Li, L. T. Pileggi, D. Newmark, and M. Sharma, “Correlation-aware statistical timing analysis with non-Gaussian delay distributions,” in Proceedings of the 42nd Design Automation Conference, 13–17 June 2005, pp. 77–82.CrossRefGoogle Scholar
  51. 51.
    Z. Feng and P. Li, “A methodology for timing model characterization for statistical static timing analysis,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design ICCAD 2007, 4–8 Nov. 2007, pp. 725–729.Google Scholar
  52. 52.
    A. B. Kahng, “Key directions and a roadmap for electrical design for manufacturability,” in Proceedings of the ESSCIRC 33rd European Solid State Circuits Conference, 11–13 Sept. 2007, pp. 83–88.Google Scholar
  53. 53.
    W. Yang, M. V. Dunga, X. Xi, J. He, W. Liu, M. C. Kanyu, X. Jin, J. J. Ou, M. Chan, A. M. Niknejad, and C. Hu, “BSIM4.6.2 MOSFET model – User’s Manual,” Department of Electrical Engineering and Computer Sciences, http://www-device.eecs.berkley.edu/ bsim3/BSIM4/BSIM462/ doc/BSIM462_Manual.pdf.
  54. 54.
    S. Tsujikawa and J. Yugami, “Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics,” IEEE Trans. Electron Devices, vol. 53, no. 1, pp. 51–55, Jan. 2006.Google Scholar
  55. 55.
    A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, and M. A. Alam, “Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2143–2154, Sept. 2007.Google Scholar
  56. 56.
    H. Kufluoglu and M. A. Alam, “A generalized reaction-diffusion model with explicit H {H}_{2} dynamics for negative-bias temperature-instability (NBTI) degradation,” IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 1101–1107, May 2007.CrossRefGoogle Scholar
  57. 57.
    S. Mahapatra, P. Bharath Kumar, T. R. Dalei, D. Sana, and M. A. Alam, “Mechanism of negative bias temperature instability in CMOS devices: degradation, recovery and impact of nitrogen,” in Proceedings of IEDM Technical Digest Electron Devices Meeting IEEE International, 13–15 Dec. 2004, pp. 105–108.Google Scholar
  58. 58.
    C. R. Parthasarathy, M. Denais, V. Huard, G. Ribes, E. Vincent, and A. Bravaix, “New insights into recovery characteristics during PMOS NBTI and CHC degradation,” IEEE Trans. Device Mater. Rel., vol. 7, no. 1, pp. 130–137, March 2007.CrossRefGoogle Scholar
  59. 59.
    W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, and Y. Cao, “The impact of NBTI on the performance of combinational and sequential circuits,” in Proceedings of the 44th ACM/IEEE Design Automation Conference DAC ’07, 4–8 June 2007, pp. 364–369.CrossRefGoogle Scholar
  60. 60.
    A. Haggag, M. Lemanski, G. Anderson, P. Abramowitz, and M. Moosa, “Realistic projections of product fmax shift and statistics due to HCI and NBTI,” in Proceedings of the Reliability Physics Symposium 45th Annual. IEEE International, 15–19 April 2007, pp. 93–96.CrossRefGoogle Scholar
  61. 61.
    Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge University Press, Cambridge, 1998.Google Scholar
  62. 62.
    K. Bernstein, K. Carrig, C. M. Durham, and P. R. Hansen, High Speed CMOS Design Styles. Kluwer, Dordecht, 1998.MATHGoogle Scholar
  63. 63.
    Q. K. Zhu and M. Zhang, “Low-voltage swing clock distribution schemes,” in Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS 2001, vol. 4, 6–9 May 2001, pp. 418–421.Google Scholar
  64. 64.
    N. James, P. Restle, J. Friedrich, B. Huott, and B. McCredie, “Comparison of split-versus connected-core supplies in the POWER6 microprocessor,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2007), 11–15 Feb. 2007, pp. 298–299,604.Google Scholar
  65. 65.
    G. Konstadinidis, M. Tremblay, S. Chaudhry, M. Rashid, P. Lai, Y. Otaguro, Y. Orginos, S. Parampalli, M. Steigerwald, S. Gundala, R. Pyapali, L. Rarick, I. Elkin, Y. Ge, and I. Parulkar, “Architecture and physical implementation of a third generation 65 nm, 16 core, 32 thread chip-multithreading SPARC processor,” IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 7–17, Jan. 2009.Google Scholar
  66. 66.
    J. Long, J. C. Ku, S. O. Memik, and Y. Ismail, “A self-adjusting clock tree architecture to cope with temperature variations,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design ICCAD 2007, 4–8 Nov. 2007, pp. 75–82.Google Scholar
  67. 67.
    S. Sankaran, S. Arai, R. Augur, M. Beck, G. Biery, T. Bolom, G. Bonilla, O. Bravo, K. Chanda, M. Chae, F. Chen, L. Clevenger, S. Cohen, A. Cowley, P. Davis, J. Demarest, J. Doyle, C. Dimitrakopoulos, L. Economikos, D. Edelstein, M. Farooq, R. Filippi, J. Fitzsimmons, N. Fuller, S. M. Gates, S. E. Greco, A. Grill, S. Grunow, R. Hannon, K. Ida, D. Jung, E. Kaltalioglu, M. Kelling, T. Ko, K. Kumar, C. Labelle, H. Landis, M. W. Lane, W. Landers, M. Lee, W. Li, E. Liniger, X. Liu, J. R. Lloyd, W. Liu, N. Lustig, K. Malone, S. Marokkey, G. Matusiewicz, P. S. McLaughlin, P. V. McLaughlin, S. Mehta, I. Melville, K. Miyata, B. Moon, S. Nitta, D. Nguyen, L. Nicholson, D. Nielsen, P. Ong, K. Patel, V. Patel, W. Park, J. Pellerin, S. Ponoth, K. Petrarca, D. Rath, D. Restaino, S. Rhee, E. T. Ryan, H. Shoba, A. Simon, E. Simonyi, T. M. Shaw, T. Spooner, T. Standaert, J. Sucharitaves, C. Tian, H. Wendt, J. Werking, J. Widodo, L. Wiggins, R. Wisnieff, and T. Ivers, “A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL technology,” in Proceedings of the International Electron Devices Meeting IEDM ’06, 11–13 Dec. 2006, pp. 1–4.Google Scholar
  68. 68.
    C. Bittlestone, “Nanometer design effects and modeling,” ISSCC Microprocessor Design Forum, February 2005.Google Scholar
  69. 69.
    M. Kulkarni, N. S. Nagaraj, A. Marshall, and V. Le, “Impact of selective process bias (SPB) of interconnects on circuit delay,” in Proceedings of the IEEE Dallas/CAS Workshop (DCAS-04) Implementation of High Performance Circuits, 27 Sept. 2004, pp. 155–158.Google Scholar
  70. 70.
    G. Lopez, R. Murali, R. Sarvari, K. Bowman, J. Davis, and J. Meindl, “The impact of size effects and copper interconnect process variations on the maximum critical path delay of single and multi-core microprocessors,” in Proc. International Interconnect Technology Conference IEEE 2007, 4–6 June 2007, pp. 40–42.CrossRefGoogle Scholar
  71. 71.
    Y. Liu, S. R. Nassif, L. T. Pileggi, and A. J. Strojwas, “Impact of interconnect variations on the clock skew of a gigahertz microprocessor,” in Proceedings of the 37th Design Automation Conference, June 5–9, 2000, pp. 168–171.Google Scholar
  72. 72.
    U. Padmanabhan, J. M. Wang, and J. Hu, “Robust clock tree routing in the presence of process variations,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 8, pp. 1385–1397, Aug. 2008.Google Scholar
  73. 73.
    R. Y. Chen, P. Yip, G. Konstadinidis, A. Demas, F. Klass, R. Mains, M. Schmitt, and D. Bistry, “Timing window applications in UltraSPARC-IIIiTM microprocessor design,” in Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, 16–18 Sept. 2002, pp. 158–163.Google Scholar
  74. 74.
    F. O’Mahony, C. P. Yue, M. Horowitz, and S. S. Wong, “10 GHz clock distribution using coupled standing-wave oscillators,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2003), 2003, pp. 428–429,504.Google Scholar
  75. 75.
    M. Shen, L.-R. Zheng, E. Tjukanoff, J. Isoaho, and H. Tenhunen, “Concurrent chip package design for global clock distribution network using standing wave approach,” in Proceedings of the Sixth International Symposium on Quality of Electronic Design ISQED 2005, 21–23 March 2005, pp. 573–578.CrossRefGoogle Scholar
  76. 76.
    S. Chan, P. Restle, T. Bucelot, S. Weitzel, J. Keaty, J. Liberty, B. Flachs, R. Volant, P. Kapusta, and J. Zimmerman, “A resonant global clock distribution for the cell broadband-engineTMprocessor,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2008), 2008, pp. 512–513.Google Scholar
  77. 77.
    M. Sasaki, “A 9.5 GHz 6 ps-skew space-filling-curve clock distribution with 1.8 V full-swing standing-wave oscillators,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2008), 2008, pp. 518–519, 633.Google Scholar

Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  • Georgios Konstadinidis
    • 1
  1. 1.Sun MicrosystemsSanta ClaraUSA

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