Digital Delay Lock Techniques

  • Thucydides Xanthopoulos
Part of the Integrated Circuits and Systems book series (ICIR)


Digital delay locked loops are highly prevalent in integrated systems. They are essentially delay lines under feedback control that can generate derived clocks based on an input reference. Applications include clock distribution, I/O interfaces, clock generation, and frequency multiplication. Digital delay locked loops also have time-todigital conversion properties and can be used in monitoring and sensing applications.

While DLLs can be designed with digital-only methods, their design involves direct manipulation of clock signals. Therefore, additional techniques are involved as opposed to standard custom digital datapath design. This chapter presents an identification of all essential digital delay locked loop components and addresses relevant design aspects for each part. It concludes with global design issues and an overview of advanced applications.


Delay Line Phase Error Finite State Machine Delay Cell Positive Edge 
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Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  • Thucydides Xanthopoulos
    • 1
  1. 1.Cavium NetworksMarlboroUSA

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