Digital Delay Lock Techniques

  • Thucydides Xanthopoulos
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

Digital delay locked loops are highly prevalent in integrated systems. They are essentially delay lines under feedback control that can generate derived clocks based on an input reference. Applications include clock distribution, I/O interfaces, clock generation, and frequency multiplication. Digital delay locked loops also have time-todigital conversion properties and can be used in monitoring and sensing applications.

While DLLs can be designed with digital-only methods, their design involves direct manipulation of clock signals. Therefore, additional techniques are involved as opposed to standard custom digital datapath design. This chapter presents an identification of all essential digital delay locked loop components and addresses relevant design aspects for each part. It concludes with global design issues and an overview of advanced applications.

Keywords

Expense Dition Nism Cond 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    W. Dally and J. Poulton, Digital Systems Engineering. Cambridge University Press, New York, NY, 1998.MATHGoogle Scholar
  2. 2.
    M. Johnson and E. Hudson, A variable delay line PLL for CPU-coprocessor synchronization. IEEE J. Solid-State Circuits, 23(5), 1218–1223, 1988.CrossRefGoogle Scholar
  3. 3.
    C. Mead and L. Conway, Introduction to VLSI Systems. Addison Wesley, Reading, MA, 1980.Google Scholar
  4. 4.
    L. Lamport, Buridan’s principle, October 1984. [Online]. Available: http://research.microsoft.com/users/lamport/pubs/buridan.pdf
  5. 5.
    T. Chaney and C. Molnar, Anomalous behavior of synchronizer and arbiter circuits. IEEE Trans. Comput., C-22(4), 421–422, 1973.Google Scholar
  6. 6.
    H. Veendrick, The behaviour of flip-flops used as synchronizers and prediction of their failure rate. IEEE J. Solid-State Circuits, 15(2), 169–176, 1980.CrossRefGoogle Scholar
  7. 7.
    A. Drake, Fundamentals of Applied Probability Theory. McGraw-Hill, New York, 1967.MATHGoogle Scholar
  8. 8.
    Nanoscale Integration and Modeling Group, Arizona State University, Predictive technology model. [Online]. Available: http://www.eas.asu.edu/ptm.
  9. 9.
    Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. In: Proc. CICC Custom Integrated Circuits Conference, 2000, pp. 201–204.Google Scholar
  10. 10.
    W. Zhao and Y. Cao, New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans. Electron Devices, 53(11), 2816–2823, 2006.CrossRefGoogle Scholar
  11. 11.
    A. Hatakeyama, H. Mochizuki, T. Aikawa, M. Takita, Y. Ishii, H. Tsuboi, S. Fujioka, S. Yamaguchi, M. Koga, Y. Serizawa, K. Nishimura, K. Kawabata, Y. Okajima, M. Kawano, H. Kojima, K. Mizutani, T. Anezaki, M. Hasegawa, and M. Taguchi, A 256-Mb SDRAM using a register-controlled digital DLL. IEEE J. Solid-State Circuits, 32(11), 1728–1734, 1997.CrossRefGoogle Scholar
  12. 12.
    F. Lin, J. Miller, A. Schoenfeld, M. Ma, and R. Baker, A register-controlled symmetrical DLL for double-data-rate DRAM. IEEE J. Solid-State Circuits, 34(4), 565–568, 1999.CrossRefGoogle Scholar
  13. 13.
    T. Xanthopoulos, D. Bailey, A. Gangwar, M. Gowan, A. Jain, and B. Prewitt, The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor. In: Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2001), 2001, pp. 402–403.Google Scholar
  14. 14.
    S. Sidiropoulos, High performance inter-chip signalling, Ph.D. dissertation, Stanford University, 1998.Google Scholar
  15. 15.
    J. Maneatis, Design of high-speed CMOS PLLs and DLLs. In: A. Chandrakasan, W. Bowhill, and F. Fox (eds.) Design of High Performance Microprocessor Circuits, IEEE Press, New York, 2001, pp. 235–260.Google Scholar
  16. 16.
    C.-K. K. Yang, Delay-locked loops – an overview. In: B. Razavi, (ed.) Phase-Locking in High-Peformance Systems, Wiley-IEEE Press, New York, NY, 2003, pp. 13–22.Google Scholar
  17. 17.
    M.-J. Lee, W. Dally, T. Greer, H.-T. Ng, R. Farjad-Rad, J. Poulton, and R. Senthinathan, Jitter transfer characteristics of delay-locked loops – theories and design techniques. IEEE J. Solid-State Circuits, 38(4), 614–621, 2003.CrossRefGoogle Scholar
  18. 18.
    J. Burnham, G.-Y. Wei, C.-K. K. Yang, and H. Hindi, A comprehensive phase-transfer model for delay-locked loops. In: Proc. IEEE Custom Integrated Circuits Conference CICC ’07, 2007, pp. 627–630.Google Scholar
  19. 19.
    J. Lee, K. Kundert, and B. Razavi, Analysis and modeling of bang-bang clock and data recovery circuits. IEEE J. Solid-State Circuits, 39(9), 1571–1580, 2004.CrossRefGoogle Scholar
  20. 20.
    J. Sonntag and J. Stonick, A digital clock and data recovery architecture for multi-gigabit/s binary links. IEEE J. Solid-State Circuits, 41(8), 1867–1875, 2006.CrossRefGoogle Scholar
  21. 21.
    G.-K. Dehng, J.-M. Hsu, C.-Y. Yang, and S.-I. Liu, Clock-deskew buffer using a SAR-controlled delay-locked loop. IEEE J. Solid-State Circuits, 35(8), 1128–1136, 2000.CrossRefGoogle Scholar
  22. 22.
    T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, S. Nakazawa, E. Kakehashi, J. Drynan, M. Komuro, T. Fukase, H. Iwasaki, M. Takenaka, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, I. Yoshida, K. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, S. Kikuchi, K. Koyama, Y. Fukuzo, and T. Okuda, A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay. IEEE J. Solid-State Circuits, 31(11), 1656–1668, 1996.Google Scholar
  23. 23.
    K. Sung and L.-S. Kim, A high-resolution synchronous mirror delay using successive approximation register. IEEE J. Solid-State Circuits, 39(11), 1997–2004, 2004.CrossRefGoogle Scholar
  24. 24.
    A. Efendovich, Y. Afek, C. Sella, and Z. Bikowsky, Multifrequency zero-jitter delay-locked loop. IEEE J. Solid-State Circuits, 29(1), 67–70, 1994.CrossRefGoogle Scholar
  25. 25.
    B. Mesgarzadeh, Low-power low-jitter clock generation and distribution, Ph.D. dissertation, Linkoping University, 2008.Google Scholar
  26. 26.
    T. Lee, K. Donnelly, J. Ho, J. Zerbe, M. Johnson, and T. Ishikawa, A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM. IEEE J. Solid-State Circuits, 29(12), 1491–1496, 1994.Google Scholar
  27. 27.
    B. Garlepp, K. Donnelly, J. Kim, P. Chau, J. Zerbe, C. Huang, C. Tran, C. Portmann, D. Stark, Y.-F. Chan, T. Lee, and M. Horowitz, A portable digital DLL for high-speed CMOS interface circuits. IEEE J. Solid-State Circuits, 34(5), 632–644, 1999.CrossRefGoogle Scholar
  28. 28.
    J.-B. Lee, K.-H. Kim, C. Yoo, S. Lee, O.-G. Na, C.-Y. Lee, H.-Y. Song, J.-S. Lee, Z.-H. Lee, K.-W. Yeom, H.-J. Chung, I.-W. Seo, M.-S. Chae, Y.-H. Choi, and S.-I. Cho, Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin x16 DDR SDRAM. In: Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2001), 2001, pp. 68–69, 431.Google Scholar
  29. 29.
    W.-J. Yun, H. W. Lee, D. Shin, S. D. Kang, J. Y. Yang, H. O. Lee, D. U. Lee, S. Sim, Y. J. Kim, W. J. Choi, K. S. Song, S. H. Shin, H. H. Choi, H. W. Moon, S. W. Kwack, J. W. Lee, Y. K. Choi, N. K. Park, K. W. Kim, Y. J. Choi, J.-H. Ahn, and Y. S. Yang, A 0.1-to-1.5GHz 4.2mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66nm CMOS technology. In: Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2008), 2008, pp. 282–283, 613.Google Scholar
  30. 30.
    C.-N. Chuang and S. luan Liu, A 40GHz DLL-based clock generator in 90nm CMOS technology. In: Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2007), 2007, pp. 178–179, 595.Google Scholar
  31. 31.
    R. Farjad-Rad, W. Dally, H.-T. Ng, R. Senthinathan, M.-J. Lee, R. Rathi, and J. Poulton, A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. IEEE J. Solid-State Circuits, 37(12), 1804–1812, 2002.CrossRefGoogle Scholar
  32. 32.
    B. Helal, M. Straayer, G.-Y. Wei, and M. Perrott, A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance. IEEE J. Solid-State Circuits, 43(4), 855–863, 2008.CrossRefGoogle Scholar
  33. 33.
    S. Sidiropoulos and M. Horowitz, A semidigital dual delay-locked loop. IEEE J. Solid-State Circuits, 32(11), 1683–1692, 1997.CrossRefGoogle Scholar
  34. 34.
    D. Stauffer et al., High Speed Serdes Devices and Applications. Springer Science and Business Media, New York, 2008.Google Scholar
  35. 35.
    K. Woo, S. Meninger, T. Xanthopoulos, E. Crain, and D. Ham, Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring. In: Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2009), 2009, pp. 68–69.Google Scholar

Copyright information

© Springer-Verlag US 2009

Authors and Affiliations

  • Thucydides Xanthopoulos
    • 1
  1. 1.Cavium NetworksMarlboroUSA

Personalised recommendations