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Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS

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Abstract

As already explained in the introduction to Chap. , the development of economically feasible nanoelectronic systems requires a tight interplay between materials and fabrication technologies on the one hand and design technologies on the other. In particular, it is quite essential to explore circuit-level measures to mitigate the limitations of process variations (PVs), leakage, and reduced device reliability and, finally, to explore system-level design approaches that are better adapted to the constraints imposed by the materials, technology, and device physics. This chapter largely deals with some of these key questions that relate to design technologies for nanoelectronic systems.

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Authors and Affiliations

  1. Microelectronic Systems Lab, EPFL – Swiss Federal Institute of Technology, 1015, Lausanne, Switzerland

    Haykel Ben Jamaa, Bahman Kheradmand Boroujeni, Giovanni De Micheli, Yusuf Leblebici, Alexandre Schmid & Milos Stanisavljevic

  2. CSEM – Swiss Center for Electronics and Microtechnology Inc.,, Neuchâtel, Switzerland

    Christian Piguet

Authors
  1. Haykel Ben Jamaa
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  2. Bahman Kheradmand Boroujeni
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  3. Giovanni De Micheli
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  4. Yusuf Leblebici
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  5. Christian Piguet
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  6. Alexandre Schmid
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  7. Milos Stanisavljevic
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Jamaa, H.B. et al. (2009). Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS. In: Nanosystems Design and Technology. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0255-9_3

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  • DOI: https://doi.org/10.1007/978-1-4419-0255-9_3

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  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-0254-2

  • Online ISBN: 978-1-4419-0255-9

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