Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS

  • Haykel Ben Jamaa
  • Bahman Kheradmand Boroujeni
  • Giovanni De Micheli
  • Yusuf Leblebici
  • Christian Piguet
  • Alexandre Schmid
  • Milos Stanisavljevic


As already explained in the introduction to Chap. , the development of economically feasible nanoelectronic systems requires a tight interplay between materials and fabrication technologies on the one hand and design technologies on the other. In particular, it is quite essential to explore circuit-level measures to mitigate the limitations of process variations (PVs), leakage, and reduced device reliability and, finally, to explore system-level design approaches that are better adapted to the constraints imposed by the materials, technology, and device physics. This chapter largely deals with some of these key questions that relate to design technologies for nanoelectronic systems.


Threshold Voltage Critical Path Nanowire Array Delay Variation Leakage Power 
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Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Haykel Ben Jamaa
    • 1
  • Bahman Kheradmand Boroujeni
    • 1
  • Giovanni De Micheli
    • 1
  • Yusuf Leblebici
    • 1
  • Christian Piguet
    • 2
  • Alexandre Schmid
    • 1
  • Milos Stanisavljevic
    • 1
  1. 1.Microelectronic Systems LabEPFL – Swiss Federal Institute of TechnologyLausanneSwitzerland
  2. 2.CSEM – Swiss Center for Electronics and Microtechnology Inc.,NeuchâtelSwitzerland

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