Abstract
The group of units mod p k (prime p>2) is known to be cyclic for k≥1, corresponding for k=1 to Fermat’s Small Theorem: n p−1≡1 mod p (n coprime to p). If p=2 and k>2 the 2k−1 units (odd residues) require two generators, such as 3 and −1 mod 2k, since 3 is semi-primitive root of 1 mod 2k. So each residue n≡±3i2j mod 2k with unique non-negative i<2k−2, j≤k. For engineering purposes this yields efficient log-arithmetic with dual base 2 and 3.
Under European ESPRIT research project HSLA “High Speed Log-Arithmetic” (main contractor Univ.Newcastle/EECE), a 32 bit VLSI microprocessor based on the binary logarithmic number system (LNS) was developed. Following a phase-1 ESPRIT feasibility study lead by J.N.Coleman, it was designed at Philips Research Labs (Eindhoven, NL) by Chris Softley and produced at Philips Semiconductors (Nijmegen NL, in 0.18 μm CMOS, 13 mm2, 150 mW at 150 MHz).
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
References
N.G. Kingsbury, P.J. Rayner: “Digital Filtering Using Logarithmic Arithmetic”, Electron. Lett. 7, 56–58 (1971)
T. Kurokawa, J.A. Payne, S.C. Lee: “Error Analysis of Recursive Digital Filters Implemented with Logarithmic Number Systems”, IEEE Trans. ASSP 28, 706–715 (1980)
E.E. Swartzlander, D.V. Chandra, H.T. Nagle, S.A. Starks: “Sign/Logarithm Arithmetic for FFT Implementation”, IEEE Trans. Comput. TC-32, 526–534 (1983) and comments TC-35, 482–484 (1986)
E.E. Swartzlander, A.G. Alexopoulos: “The Sign/Logarithm Number System”, IEEE Trans. Comput. TC-24, 1238–1242 (1975)
F.J. Taylor, R. Gill, J. Joseph, J. Radke: “A 20 Bit Logarithmic Number System Processor”, IEEE Trans. Comput. TC-37, 190–200 (1988)
L.K. Yu, D.M. Lewis: “A 30-b Integrated Logarithmic Number System Processor”, IEEE JSSC 26, 1433–1440 (1991)
D.M. Lewis: “Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit”, IEEE Trans. Comput. TC-43, 974–982 (1994)
D.M. Lewis: “114 MFLOPS Logarithmic Number System Arithmetic Unit for DSP Applications”, IEEE JSSC 30, 1547–1553 (1995)
M. Arnold, T. Bailey, J. Cowles, M. Winkel: “Arithmetic Co-Transformations in Real and Complex Logarithmic Number Systems”, IEEE Trans. Comput. TC-47, 777–786 (1998)
M.G. Arnold : “Applying Features of IEEE 754 to Sign/Logarithm Arithmetic”, IEEE Trans. Comput. TC-41, 1040–1050 (1992)
J.N. Coleman: “Simplification of Table Structure in Logarithmic Arithmetic”, Electron. Lett. 31, 1905–1906 (1995) (Erratum p. 2103 (1996))
M. Schulte, J. Stine: “Symmetric Bipartite Tables for Accurate Function Approximation”, Proceedings of the 13th Symposium on Computer Arithmetic, 1997
J.N. Coleman, E.I. Chester: “A 32-Bit Logarithmic Arithmetic Unit and Its Performance Compared to Floating-Point”, 14th Symposium on Computer Arithmetic (1999).
Texas Instruments: “TMS320C6711 Floating Point DSP” (1997). http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?family=dsp§ionId=2&tabId=135&familyId=327
E.E. Swartzlander: “Merged Arithmetic”, IEEE Trans. Comput. TC-29, 946–950 (1980)
W.H. Press: “Numerical Recipes in Pascal”, Cambridge University Press, Cambridge, 1989
J.N. Coleman, E.I. Chester, C.I. Softley, J. Kadlec: “Arithmetic on the European Logarithmic Microprocessor”, IEEE Trans. Comput. TC-49 (7), 702–715 (2000).
F. Albu et al.: “The Gauss-Seidel Fast Affine Projection Algorithm”, IEEE Workshop Signal Processing, Systems Design and Implementation (SIPS), 109–114, CA, USA, 2002
J.N. Coleman et al.: “The European Logarithmic Microprocessor—a QR RLS application”, IEEE 35th Asilomar Conference on Signals, Systems and Computers, 155–159, CA, USA, 2001
J. Kadlec, A. Hermanek, Ch. Softley, R. Matousek, M. Licko: “32-bit Logarithmic ALU for Handel-C-2.1 and Celoxica DK1”, UTIA Prague: Inst. Info-Th. and Automation (dpt. Signal Proc.). http://napier.ncl.ac.uk/elm/Docs/Lns2CelRev2.pdf
J. Coleman, C. Softley, J. Kadlec, R. Matousek, Z. Pohl, A. Hermanek, N. Benschop: “The European Logarithmic Microprocessor”, IEEE Trans. Comput. TC-57 (4), 532–546 (2008).
N.F. Benschop: Patent US-5923888 “Multiplier for the Multiplication of at Least two Figures in an Original Format” (1999). See also http://de.arxiv.org/abs/math.GM/0105029
K. Hwang: “Computer Arithmetic”, (p. 164), Wiley, New York, 1979
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2009 Springer Science + Business Media B.V.
About this chapter
Cite this chapter
Benschop, N.F. (2009). Log-Arithmetic, with Single and Dual Base. In: Associative Digital Network Theory. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-9829-1_11
Download citation
DOI: https://doi.org/10.1007/978-1-4020-9829-1_11
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-9828-4
Online ISBN: 978-1-4020-9829-1
eBook Packages: Computer ScienceComputer Science (R0)