Supporting Dynamic Application Patterns
To efficiently utilize the large number of transistors that are available on the chip with manageable design complexity and wiring requirements, Chip Multiprocessors (CMPs) have been recently proposed (Tylor et al., IEEE Micro, April 2002; Mai et al., Proc. ISCA, June 2000; Sankaralingam et al., IEEE Micro, November/December 2003; Kalla et al., IEEE Micro, March/April 2004). In CMPs, the chip area is divided into a number of regular and identical tiles, where each tile represents a processor/memory core. The use of a simpler architecture for the processor in a single tile, coupled together with the reuse of the tile across the chip, results in a reduced design complexity, when compared to conventional single-core processor systems.
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