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Rapid Prototyping of the Soft IP Cores on FPGA

  • Rajanish K. Kamat
  • Santhosh A. Shinde
  • Vinod G. Shelake

According to the SIA Technology Roadmap, by the end of this decade the semiconductor industry will manufacture chips with four billion transistors, thousands of pins, and clock speeds of 10 GHz. In order to increase design productivity, a new design flow has recently emerged, based on the reuse of portable IP cores. An IP core is a block of logic or data that is used with a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). The increasing gap between design productivity and chip complexity, and emerging System-on- Chip (SoC) have led to the wide utilization of reusable intellectual property (IP) cores [79]. For an SoC chip, the validation of hardware, software, and firmware on a common platform can be accomplished using FPGA-based prototypes. FPGA prototypes make it possible for SoC designs to be delivered on time, on budget, and on market target [77]. The reward of FPGA based prototyping is getting better designs sooner, in which hardware and software components are integrated before final silicon. Today, the electronic system design community is mainly concerned with defining efficient System-on-Chip (SoC) design methodologies in order to benefit from the high integration capabilities of current FPGA technologies on the one hand, and manage the increasing algorithmic complexity of applications on the other hand. Rapid prototyping is considered as a key to speed up the system design [78]. The popularity of the FPGA based prototyping is evident from the survey commissioned by Synplicity® Inc. in December 2004, wherein more than 20,000 developers around the world were questioned as to their hardware-assisted ASIC verification strategy. The results showed that 1/3 of today's ASIC designs are verified by means of an FPGA-based prototype [80]. Thus, it is becoming increasingly necessary to create prototypes of ASIC designs that run ‘at speed' in the context of the system. The most cost effective technique emerged out to achieve this level of performance is to create an FPGA-based prototype.

Keywords

Intellectual Property Rapid Prototype Field Programmable Gate Array Fuzzy Controller Finite State Machine 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2009

Authors and Affiliations

  • Rajanish K. Kamat
    • 1
  • Santhosh A. Shinde
    • 1
  • Vinod G. Shelake
    • 1
  1. 1.Department of ElectronicsShivaji UniversityKolhapurIndia

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