Planar Double-Gate Transistor pp 27-54 | Cite as

# Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach

The bulk MOSFET scaling has recently encountered significant limitations, mainly related to the gate oxide (SiO_{2}) leakage currents [1, 2], the large increase of parasitic short channel effects (SCEs) and the dramatic mobility reduction [3, 4] (due to highly doped Silicon channels precisely used to reduce these short channel effects). Technological solutions have been proposed in order to continue to use the “bulk solution” until the 32 nm ITRS node. Most of these solutions envisage the introduction of high-permittivity gate dielectric stacks (to reduce the gate leakage, [2, 5, 6]), midgap metal gate (to suppress the Silicon gate polydepletion-induced parasitic capacitances) and strained materials-based channel (to increase carrier mobility [7–9]). In parallel to these efforts, alternative solutions to replace the conventional bulk architecture have been proposed and studied in the recent literature, such as the introduction of new device architecture (e.g. multiple-gate devices, Silicon nanowires MOSFET). Ultra-thin film body Double-Gate (DG) structures become to be envisaged as a possible alternative to the conventional devices, due to its enormous potentiality to push back the integration limits to which conventional bulk transistor are subjected [10–13]. The main advantage of this architecture is to offer a reinforced electrostatic coupling between the conduction channel and the gate electrode. In other terms, a double-gate structure can efficiently sandwich (and thus very well control, electrostatically speaking) the semiconductor element playing the role of the transistor channel, which can be a Silicon thin layer or nanowire. In this way, Double-Gate devices could be designed with intrinsic channels, offering then an enhanced mobility, the elimination of doping fluctuations and a high probability of ballistic transport. Further, for the symmetrical DG device, the condition of “volume inversion” [14] can be beneficial with regard to carrier mobility and source-drain transport. In spite of excellent electrical performances due to its multiple conduction surfaces, conventional DG MOSFET allows only three-terminal operation because the two gates are tied together. DG structures with independent gates have been recently proposed [15–19], allowing a four terminal operation. Independent Double-Gate (IDG) MOSFETs offer additional potentialities, such as a dynamic threshold voltage control by one of the two gates and transconductance modulation in addition to the conventional switching operation [15,16].

Although the operation of DG transistor is similar to the conventional MOSFET, the physics of DG and IDG MOSFETs is more complicated. Moreover, physical phenomena such as 2D electrostatics or carrier quantum confinement have to be considered, since these structures will be precisely used to design very integrated devices (with short channels and ultra thin films). Therefore, new compact models, dedicated to circuit simulation, have to be developed for DG and IDG MOSFETs. Nanoscale DG and IDG MOSFETs introduce challenges to compact modeling associated with the enhanced coupling between the electrodes (source, drain, and gates), quantum confinement, ballistic or quasi-ballistic transport, gate tunneling current, etc. [20]. In the case of IDG MOSFET, the modeling task is even more difficult due to the influence of the second gate which can be independently switched. For DG MOSFET devices, drain current compact models can in general be surface potential or charge based. Most models presented to date are developed for undoped devices with a long enough channel to assume that the transport is mainly governed by the drift-diffusion mechanism [21–30]. Regarding the modeling of the electrostatics, most of the work has been based on solving one-dimensional (1-D) Poisson's equation perpendicular to the gates, thereby neglecting SCEs. For example, Taur [21,22] developed a framework of two equations to describe the electrostatic potential in the Silicon film of the DG MOSFET. Charge-based drain—current models have been developed by He et al. [27] and Sallese et al. [28] to avoid the numerical solution of the transcendental equation used in the surface potential-based models. Recently, a unified model for DG MOSFETs was derived by Taur et al. [23] based on the Pao— Sah's integral [31]. Ortiz-Conde et al. [24,29] have also proposed a surface potential based drain—current model for DG MOSFETs, which was an extension of their previously proposed Lambert function based analytic solution for the surface potential of single-gate undoped-body bulk devices [32]. These models considered the classical (i.e. without quantum effects) drain current in long channels (i.e. neglecting SCE) DG MOSFETs. However SCE is an important issue for these ultra-scaled devices. Liang and Taur proposed in [33] a drain current model for short channel DG MOSFETs, but this model only applies in subthreshold regime, where the assumption of a negligible mobile-charge sheet density can be used for simplifying the solving of the two-dimensional (2-D) Poisson's equation. A conventional technique used to take into account SCE is to add the SCEs as a second-order correction using fitting parameters. An alternative solution is the technique based on conformal mapping for obtaining analytical solutions of the 2-D Poisson's equation, whereby the SCEs are inherently included without the need of additional fitting parameters [34–38].

## Keywords

Threshold Voltage Drain Current Compact Modeling Ballistic Transport IEEE Electron Device## Preview

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