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Radiation Effects on SRAM-Based FPGAs

Modeling and simulation of radiations effects
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 26)

The past 30 years have seen the discovery that electronic circuits are sensitive to transient effects such as Single Event Upsets (SEUs) provoked by ionizing radiation [1]. Since the discovery of SEUs at aircraft altitudes, researchers have made significant efforts to monitor the environment. The space and the earth environment contain various ionizing radiations, generated by natural phenomena such as sun activity and manmade radiation that interacts with silicon atoms. If, at ground level, neutrons and alpha particles are the most frequent causes of SEUs, in a space environment, they are protons and heavy ions. When a particle hits the surface of a silicon area, it loses its energy through the production of free electron-hole pairs, resulting in a dense ionized track in the struck region [2]. Interestingly, when the struck silicon area implements a static memory cell, the transient pulse may induce permanent changes: it can indeed activate the inversion of the stored value. In SRAM-based FPGAs, transient faults originating in the FPGAs configuration memory have dramatic effects since the circuits the FPGAs implement are totally controlled by the content of the configuration memory, which is composed of static RAM cells [3, 4]. In this chapter, the effects of the SEUs within the configuration memory of SRAM-based FPGAs will be accurately described, thanks to the graph model presented in the previous chapter, the effects of SEUs within the internal FPGA’s resources is modeled and analyzed.

Keywords

Application Layer Device Under Test Logic Resource FPGA Device Triple Modular Redundancy 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    T. P. Ma, P. V. Dressendorfer, Ionizing Radiation Effects in MOS Devices and Circuits, Wiley, New York, 1989, ISBN: 0-471-84893-X.Google Scholar
  2. 2.
    J. L. Barth, C. S. Dyer, E. G. Stassinopoulos, Space, Atmospheric, and Terrestrial Radiation Environments, IEEE Transaction on Nuclear Science, Vol. 50, No. 3, June 2003, pp. 466–482.CrossRefGoogle Scholar
  3. 3.
    M. Ceschia, A. Paccagnella, S. -C. Lee, C. Wan, M. Bellato, M. Menichelli, A. Papi, A. Kaminski, J. Wyss, Ion Beam Testing of ALTERA APEX FPGAs, NSREC 2002 Radiation Effects Data Workshop Record, Phoenix, AZ, July 2002.Google Scholar
  4. 4.
    R. Katz, K. LaBel, J. J. Wang, B. Cronquist, R. Koga, S. Penzin, G. Swift, Radiation Effects on Current Field Programmable Technologies, IEEE Transaction on Nuclear Science, Vol. 44, No. 6, Dec. 1997, pp. 1945–1956.CrossRefGoogle Scholar
  5. 5.
    Jih-Jong Wang, Brian E. Cronquist, Benny Sin, Jennifer J. Moriarta, Richard B. Katz, Antifuse FPGA for space applications, RADECS 1997.Google Scholar
  6. 6.
    R. Koga, S. Penzin, K. Crawford, W. Crain, Single Event Functional Interrupt (SEFI) Sensitivity in Microcircuits, the Aerospace Corporation, 1998.Google Scholar
  7. 7.
    M. Wirthlin, E. Johnson, N. Rollins, M. Caffrey, P. Graham, The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003, pp. 133–142.Google Scholar
  8. 8.
    E. Fuller, M. Caffrey, A. Salazar, C. Carmichael, J. Fabula, Radiation Testing Update, SEU Mitigation and Availability Analysis of the Virtex FPGA for Space Re-configurable Computing, presented at the IEEE Nuclear and Space Radiation Effects Conference, July 2000.Google Scholar
  9. 9.
    M. Bellato, M. Ceschia, M. Menichelli, A. Papi, J. Wyss, A. Paccagnella, Ion Beam Testing of SRAM-Based FPGA’s, IEEE Radiation Effects Data Workshop, July 2002.Google Scholar
  10. 10.
    M. Alderighi, F. Casini, S. D’Angelo, F. Faure, M. Mancini, S. Pastore, G. R. Sechi, R. Velazco, Radiation Test Methodology of SRAM-Based FPGAs by Using THESIC+, IEEE 9th On-Line Testing Symposium, 2003, pp. 162.Google Scholar
  11. 11.
    M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Cerchia, A. Paccagnella, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin, Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA, IEEE Design Automation and Test in Europe, 2004, pp. 188–193.Google Scholar
  12. 12.
    B. L. Bhuva, J. J. Paulos, R. S. Gyurcsik, S. E. Kerns, Switch-Level Simulation of Total Dose Effects on CMOS VLSI Circuits, IEEE Transaction on Computer-Aided Design, Vol. 8, No. 9, Sept. 1989, pp. 933–938.CrossRefGoogle Scholar
  13. 13.
    M. P. Baze, S. Buchner, W. G. Bartholet, T. A. Dao, An SEU Analysis Approach for Error Propagation in Digital VLSI CMOS ASICs, IEEE Transaction Nuclear Science, Vol. 42, No. 6, Dec. 1995, pp. 1863–1869.CrossRefGoogle Scholar
  14. 14.
    M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori, Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs, IEEE Transaction on Nuclear Science, Vol. 50, No. 6, Dec. 2003, pp. 2088–2094.CrossRefGoogle Scholar
  15. 15.
    R. Velazco, S. Rezgui, R. Ecoffet, Predicting Error Rate for Microprocessor-Based Digital Architectures Through C.E.U. (Code Emulating Upsets) Injection, IEEE Transaction Nuclear Science, Vol. 47, Dec. 2000, pp. 2405–2411.CrossRefGoogle Scholar
  16. 16.
    J. Rose, A. El Gamal, A. Sangiovanni-Vincetelli, Architecture of Field-Programmable Gate Arrays, IEEE Proceedings, Vol. 81, No. 7, July 1993, pp. 1013–1029.CrossRefGoogle Scholar
  17. 17.
    F. Lima, C. Carmichael, J. Fabula, R. Padovani, R. Reis, A Fault Injection Analysis of Virtex FPGA TMR Design Methodology, IEEE European Conference on Radiation and Its Effect on Component and Systems, 2001, pp. 275–282.Google Scholar
  18. 18.
    M. Alderighi, F. Casini, S. D’Angelo, M. Mancini, A. Marmo, S. Pastore, G. R. Sechi, A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs, 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 71–78.Google Scholar
  19. 19.
    M. Alderighi, S. D’Angelo, M. Mancini, G. R. Sechi, A Fault Injecting Tool for SRAM-Based FPGA, 9th IEEE On-Line Testing Symposium, 2003, pp. 129–133.Google Scholar
  20. 20.
    C. Carmichael, M. Caffrey, A. Salazar, Correcting Single-Event Upset Through Virtex Partial Reconfiguration, Xilinx Application Notes, XAPP216, 2000.Google Scholar
  21. 21.
    C. Carmichael, Triple Module Redundancy Design Techniques for Virtex FPGAs, Xilinx Application Notes, XAPP197, 2001.Google Scholar
  22. 22.
    F. Lima, L. Carro, R. Reis, Designing Fault Tolerant System into SRAM-Based FPGAs, IEEE/ACM Design Automation Conference, June 2003, pp. 650–655.Google Scholar
  23. 23.
    Xilinx Inc., Spartan-II 2.5 V FPGA Family: Introduction and Ordering Information, Xilinx Product Specification Datasheets, 2003.Google Scholar
  24. 24.
    M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. S. Reorda, A. Paccagnella, Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs, IEEE Transactions on Nuclear Science, Vol. 51, No. 6, Dec. 2004, pp. 3354–3359.CrossRefGoogle Scholar

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