The growing consumer demands for more functionality has lead to an increase in size and complexity of the final implementation of such designs. The semiconductor industry's ability to reduce the minimum feature sizes of integrated circuits has so far supported these growing consumer demands. This fast pace of increase in integration of devices per unit area on silicon, commonly known as the Moore's Law  (Figure 1.1), is expected to continue up to the next ten years, roughly doubling the devices per chip every eighteen to twenty-four months . However, even though current silicon technology is closely following the growing demands; the effort needed in modeling, simulating, and validating such designs is adversely affected. This is because current modeling tools and frameworks, hardware and software co-design environments, and validation and verification frameworks do not scale with the rising demands.
Fortunately, the electronic design automation (EDA) industry has historically played an integral role in providing engineers with the support for these challenging demands. For example, the introduction of register transfer level (RTL) as a higher abstraction layer  over schematics in traditional hardware description languages (HDL)s such as Verilog and VHDL. The RTL abstraction layer is nowadays accepted as the de-facto abstraction layer for describing hardware designs. However, in recent years, the EDA community is again pushing the abstraction layer a notch higher by promoting the electronic system level (ESL) layer for addressing the lack of scalable tools, frameworks and design methods. So far, the accepted definition of ESL is “a level above RTL including both hardware and software design” as suggested by The International Technology Roadmap for Semiconductors in 2004 . However, there is a lack of consensus in the EDA community as to what this next level is to be.
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