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Digitally Programmable Delay

  • Nuno Paulino
  • Adolfo Steiger Garção
  • João Goes
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

this chapter deals with the problem of generating a clock signal with a programmable delay. This clock is necessary in the radar system to define the sampling instant in the receiver channel. The delay in this clock signal is relative to the transmit clock signal and is used to determine the target distance. A new digitally programmable delay architecture that can have a large programming linearity is proposed. This architecture is based on a digital ΣΔ modulator that controls a 1-bit digital to time converter, whose output is filtered by a delay lock-loop, thus producing the delayed clock signal. This architecture is analyzed and designed, at high level, to meet the required specifications for the radar system. A high level model is used to simulate the behavior of this circuit and validate the design. The electronic sub-blocks necessary to build this circuit are described, analyzed and design methodology for each sub-block is derived. These circuits are implemented using differential clock signals in order to reduce the noise level in the radar system.

Keywords

Parasitic Capacitance Clock Signal Differential Pair Reference Clock Common Mode Voltage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2008

Authors and Affiliations

  • Nuno Paulino
    • 1
  • Adolfo Steiger Garção
    • 1
  • João Goes
    • 1
  1. 1.Depto. Engenharia ElectronicaUniversidade Nova de Lisboa Fac. Ciencias e TecnologiaQuinta da TorrePortugal

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