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NAND Flash memories

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Bibliography

  • D. S. Byeon et al, “An 8Gb Multi-level NAND Flash Memory with 63 nm STI CMOS Process technology”, ISSCC 2005 Digest of Technical Papers, pp. 46–47.

    Google Scholar 

  • T. Cho et al., “A 3.3 V 1 Gb Multi-level NAND Flash Memory with Non-uniform Threshold Voltage Distribution”, ISSCC 2001 Digest of Technical Papers, pp. 28–29.

    Google Scholar 

  • Y.-J. Choi, K.-D. Suh, Y.-N. Koh, J.-W. Park, K.-J. Lee, Y.-J. Cho, B.-H. Suh, “A High Speed Programming Scheme for Multi-Level NAND Flash Memory”, in 1996 Symposium VLSI Circuits Dig. Tech. Papers., pp. 170–171, June 1996.

    Google Scholar 

  • T. Cho, Y.-T. Lee, E.-C. Kim, J.-W. Lee, S. Choi, S. Lee, D.-H. Kim, W.-G. Han, Y.-H. Lim, J.-D. Lee, J.-D. Choi, and K.-D. Suh. "A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 11, pp. 1700–1706, November 2001.

    Google Scholar 

  • T. Endoh et al., “A New Write/Erase Method to Improve the Read Disturb Characteristics Based on the Decay Phenomena of Stress Leakage Current for Flash Memories”, IEEE Transactions on Electron Devices, Vol. 45, No. 1, pp. 98–104, January 1998.

    Google Scholar 

  • T. Hara et al, “A 146mm/sup 2/8 Gb NAND Flash Memory with 70 nm CMOS Technology”, ISSCC 2005 Digest of Technical Papers, pp. 44–45.

    Google Scholar 

  • G. J. Hemink, T. Tanaka, T. Endoh, S. Aritome, R. Shirota, “Fast and Accurate Pro-gramming Method for Multi-Level NAND EEPROMs”, in 1995 Symposium VLSI Technology Dig. Tech. Papers., pp. 129–130, June 1995.

    Google Scholar 

  • K. Hosono et al., “A High Speed Failure Bit Counter for the Pseudo Pass Scheme (PPS) in Program Operation for Giga Bit NAND Flash”, NVMWS 2004.

    Google Scholar 

  • K. Inamiya et al., “A 130 mm2 256 Mb NAND flash with shallow trench isolation technology”, ISSCC 1999 Digest of Technical Papers, pp. 112–113.

    Google Scholar 

  • T. S. Jung, Y.-J. Choi, K.-D. Suh, B.-H. Suh, J.-K. Kim, Y.-H. Lim, Y.-N. Koh, J.-W. Park, K.-J. Lee, J.-H. Park, K.-T. Park, J.-R. Kim, J.-H. Lee, H.-K. Lim , "A 117-mm$2$ 3.3 V only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications”, IEEE Journal of Solid-State Circuits, Vol. SC-31, pp. 1575–1583, November 1996.

    Google Scholar 

  • K. Kim, "Future Outlook of NAND Flash Technology for 40 nm Node and Beyond”, NVMWS 2004.

    Google Scholar 

  • J. -D. Lee, “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation”, IEEE Electron Device Letters, Vol. 23, No. 5, pp. 264–266, May 2002.

    Google Scholar 

  • S. Lee et al, “A 3.3 V 4 Gb Four-level NAND Flash Memory with 90 nm CMOS technology”, ISSCC 2004 Digest of Technical Papers, pp. 52–53.

    Google Scholar 

  • J. Lee et al, “A 1.8 V 2 Gb NAND flash memory for mass storage applications” ISSCC 2003 Digest of Technical Papers, pp. 290–494.

    Google Scholar 

  • F. Masuoka, M. Momodomi, Y. Iwata and R. Shirota, “New Ultra High Density EPROM and Flash with NAND Structure Cell”, IEDM Tech. Dig., pp. 552–555, 1987.

    Google Scholar 

  • R. Micheloni et al. “A 4Gb 2b/Cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput”, ISSCC Dig. Tech. Papers, San Francisco, February 2006.

    Google Scholar 

  • H. Nobukata et al., “A 144-Mb, Eight-Level NAND Flash Memory with Optimized Pulsewidth Programming,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 5, pp. 682–690, May 2000.

    Google Scholar 

  • K. Sakui, "NAND Flash design” 2004 ISSCC, Memory Forum, Memory Circuit Design: Non-Volatile Memories Technology and Design.

    Google Scholar 

  • K. -D. Suh et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, pp. 1149–1156, November 1995.

    Google Scholar 

  • K. Takeuchi et al., “A 56 nm CMOS 99 mm$2$ 8 Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput” 2006 ISSCC Digest of Technical Papers, pp. 507–508.

    Google Scholar 

  • K. Takeuchi, T. Tanaka, H. Nakamura, “A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories”, IEEE Journal of Solid-State Circuits, Vol. SC-31, pp. 602–609, April 1996.

    Google Scholar 

  • K. Takeuchi, T. Tanaka, T. Tanzawa, “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 8, pp. 1228–1238, August 1998.

    Google Scholar 

  • K. Takeuchi et al., “A Negative Vth Cell Architecture for Highly Scalable, Excellent Noise Immune and High Reliable NAND Flash Memories,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 675–684, May 1999.

    Google Scholar 

  • K. Takeuchi et al., “A Source-Line Programming Scheme for Low-Voltage Operation NAND Flash Memories,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 5, pp. 672–681, May 2000.

    Google Scholar 

  • T. Tanaka et al., “A quick intelligent page-programming architecture and a shielded bitline sensing method for 3V-only NAND flash memory”, IEEE Journal of Solid-State Circuits, Vol. 29, No. 11, November 1994, pp. 1366–1373.

    Google Scholar 

  • T. Tanaka, T. Tanzawa, K. Takekuchi, “A 3.4-Mbyte/sec Programming 3-level NAND Flash Memory Saving 40% Die Size per Bit”, in 1997 Symposium VLSI Circuits Dig. Tech. Papers., pp. 65-66, June 1997.

    Google Scholar 

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Micheloni, R., Marelli, A., Ravasio, R. (2008). NAND Flash memories. In: Error Correction Codes for Non-Volatile Memories. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8391-4_4

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