Detection of stability faults in SRAM cells by the means of the functional tests can be a time consuming and expensive effort. Except for the most severe cases, SRAM cells with reduced stability may not be readily detected by the traditional memory tests. Detection faults such as the Data Retention Fault by the traditional memory tests requires extra pause periods of the order of hundreds of milliseconds for each data background used in the test sequence and/or increased temperature. The increased test time, partial test coverage and extensive silicon characterization to determine the worst-case test conditions add to the list of the drawbacks associated with the use of the traditional tests for cell stability test in SRAMs. Both the extra test time and/or the high temperature requirements add to the test cost and may become prohibitive. The SRAM IDDQ techniques, which were popular in earlier technology generations, suffer from the reducing of the diagnostic resolution in the new technology generations and fail to detect any type of data retention faults or stability faults in on an individual memory cell basis with any degree of accuracy [1].
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© 2008 Springer Science + Business Media B.V
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(2008). Techniques for Detection of SRAM Cells with Stability Faults. In: CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies. Frontiers In Electronic Testing, vol 40. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8363-1_5
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DOI: https://doi.org/10.1007/978-1-4020-8363-1_5
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