ESD Protection for Smart Power Applications
Often in compact microelectronic systems, it is necessary to combine different functional blocks on one chip to minimize the component count. These microelectronic systems are realized as integrated circuits (ICs) using a variety of technologies. One such application includes mixed power (smart power) technology combining bipolar, CMOS and DMOS (Double-diffused MOS) devices in a single chip. Today mixed technologies are capable of integrating CMOS macro-cells as complex as microcomputer cores, power transistors and nonvolatile memories. Smart power approach enables designs with a mixture of CMOS logic, low voltage analogue and high voltage drive transistors on one chip. Typical applications of smart power technology are industrial power actuators and programmable logic controllers, camera application control systems, automobile electronics and liquid crystal display (LCD) driver ICs . Since smart power ICs include low voltage devices (VDD ≈ 1.8–5 V) and high voltage devices (VDD ≈ 20–60 V), low/high voltage ESD protection devices should be integrated in the chip.
In this chapter, we will discuss ESD protection strategies of high voltage modules in smart power ICs. There are two general categories of ESD protection schemes used in I/Os: the non-self protecting scheme and the self protecting scheme. For non-self protecting scheme, it needs to add the ESD protection devices to the I/O cell. While for the self-protecting scheme, the I/O cell itself is an ESD protection device. In smart power technologies, the typica1 self protecting device is the lateral diffused MOS (LDMOS) power transistor since the device can be used as the ESD protection device and as output driver simultaneously. However, since the parasitic lateral npn bi-polar transistor is difficult to be turned-on by the ESD pulse, the grounded-gate LDMOS often suffers the ESD vulnerability. The typical nonself protecting scheme for power technologies is based on ESD high-voltage MOSFETs, silicon controlled rectifier (SCR) devices and bipolar junction transistors (BJTs).
This chapter is focused on the analyzing of ESD robustness of different power ESD protection devices, latch-up immunity and layout issues.
KeywordsTransportation Dition Protec Ectron
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