Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques

  • Daniel Große
  • Hernan Peraza
  • Wolfgang Klingauf
  • Rolf Drechsler
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 10)


The system description language SystemC enables to quickly create executable specifications at adequate levels of abstraction for both hardware/software integration and fast design space exploration. Besides the modelling of a system, verification has become a dominant factor in circuit and system design. Since SystemC is a versatile language based on C++, testbenches at different abstraction levels can easily be built. But the fault coverage of a manually developed testbench is hard to quantify. In this paper, an approach for measuring the quality of SystemC testbenches is presented. The approach is based on dedicated code coverage techniques and identifies all the parts of a SystemC model that have not been tested. Experimental results show the applicability of our methodology.


SystemC Testbench Quaility Coverage 


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Copyright information

© Springer Science + Business Media B.V 2008

Authors and Affiliations

  • Daniel Große
    • 1
  • Hernan Peraza
    • 1
  • Wolfgang Klingauf
    • 2
  • Rolf Drechsler
    • 1
  1. 1.Institute for Computer ScienceUniversity of BremenBremenGermany
  2. 2.Department E.I.S.Technical University of BraunschweigBraunschweigGermany

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