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Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques

  • Daniel Große
  • Hernan Peraza
  • Wolfgang Klingauf
  • Rolf Drechsler
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 10)

Abstract

The system description language SystemC enables to quickly create executable specifications at adequate levels of abstraction for both hardware/software integration and fast design space exploration. Besides the modelling of a system, verification has become a dominant factor in circuit and system design. Since SystemC is a versatile language based on C++, testbenches at different abstraction levels can easily be built. But the fault coverage of a manually developed testbench is hard to quantify. In this paper, an approach for measuring the quality of SystemC testbenches is presented. The approach is based on dedicated code coverage techniques and identifies all the parts of a SystemC model that have not been tested. Experimental results show the applicability of our methodology.

Keywords

SystemC Testbench Quaility Coverage 

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References

  1. 1.
    B. Beizer. Software Testing Techniques. Wiley, New York, 1990.Google Scholar
  2. 2.
    L. Cai and D. Gajski. Transaction level modeling: an overview. In CODES+ ISSS’03, pp. 19–24, 2003Google Scholar
  3. 3.
    R. Drechsler, G. Fey, C. Genz, and D. Große. SyCE: An integrated environment for system design in SystemC. In IEEE International Workshop on Rapid System Prototyping, pp. 258–260, 2005Google Scholar
  4. 4.
    EmViD: Embedded Video Detection. http://www.greensocs.com/GreenBench/EmViD.
  5. 5.
    G. Fey, D. Große, T. Cassens, C. Genz, T. Warode, and R. Drechsler. ParSyC: An efficient SystemC parser. In Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 148–154, 2004Google Scholar
  6. 6.
    R. S. French, M. S. Lam, J. R. Levitt, and K. Olukotun. A general method for compiling event-driven simulations. In Design Automation Conference, pp. 151–156, 1995Google Scholar
  7. 7.
  8. 8.
    C. Genz and R. Drechsler. System exploration of SystemC designs. In IEEE Annual Symposium on VLSI, pp. 335–340, 2006Google Scholar
  9. 9.
    D. Große, U. Kühne, and R. Drechsler. Hw/sw coverification of embedded systems using bounded model checking. In Great Lakes Symp. VLSI, pp. 43–48, 2006Google Scholar
  10. 10.
    W. Klingauf. Systematic transaction level modeling of embedded systems with SystemC. In Design, Automation and Test in Europe, pp. 566–567, 2005Google Scholar
  11. 11.
    W. Klingauf, R. Günzel, O. Bringmann, P. Parfuntseu, and M. Burton. Greenbus: A generic interconnect fabric for transaction level modelling. In Design Automation Conference, pp. 905–910, 2006Google Scholar
  12. 12.
    S. Microelectronics. TAC: Transaction Accurate Communication. http://www.greensocs.com/TACPackage, 2005.
  13. 13.
    Open SystemC Initiative, http://www.systemc.org. SystemC 2.1 Language Reference Manual, 2005.
  14. 14.
    T. Parr. Language Translation using PCCTS and C++ : A Reference Guide. Automata Publishing, San Jose, CA, 1997Google Scholar
  15. 15.
    SystemC Verification Working Group, http://www.systemc.org. SystemC Verification Standard Specification Version 1.0e.
  16. 16.
    S. Tasiran and K. Keutzer. Coverage metrics for functional validation of hardware designs. In IEEE Design and Test of Computers, 18(4), pp. 36–45, 2001Google Scholar
  17. 17.
    J. Yuan, C. Pixley, and A. Aziz. Constraint-based Verification. Springer, New York, 2006.zbMATHGoogle Scholar

Copyright information

© Springer Science + Business Media B.V 2008

Authors and Affiliations

  • Daniel Große
    • 1
  • Hernan Peraza
    • 1
  • Wolfgang Klingauf
    • 2
  • Rolf Drechsler
    • 1
  1. 1.Institute for Computer ScienceUniversity of BremenBremenGermany
  2. 2.Department E.I.S.Technical University of BraunschweigBraunschweigGermany

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