Timed Asynchronous Circuits Modeling and Validation Using SystemC

  • Cédric Koch-Hofer
  • Marc Renaudin
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 10)


ASC is a SystemC library designed for modeling asynchronous circuits. In order to respect the semantic of asynchronous circuits, the synchronization primitives of ASC rely on SystemC immediate notification. In this paper we present a time model which allows us to properly trace ASC processes activity. This time model is not restricted to ASC and could be used to model asynchronous circuits using a CSP based modeling language. Moreover, this time model can be used for validating timed models of circuits mixing synchronous and asynchronous parts. This time model is therefore used for designing the tracing facilities of ASC. This paper also presents a patch of the OSCI SystemC simulator allowing to properly validate ASC models. As relevant examples, two versions of the Octagon interconnect are modeled and verified using the ASC library.


Asynchronous Circuits SystemC Time Model Simulation and Validation 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Jantsch A, Tenhunen H (2003) Networks on chip. Kluwer, Boston, MAGoogle Scholar
  2. 2.
    Sparsø J, Furber S (2001) Principles of asynchronous circuit design. Kluwer, Boston, MAGoogle Scholar
  3. 3.
    Nielsen SF, Sparsø J (2001) Analysis of low-power SoC interconnection networks. In: 19th Norchip, pp 77–86Google Scholar
  4. 4.
    Edwards DA, Toms WB (2004) Design, Automation and Test for Asynchronous Circuits and Systems. Technical Report IST-1999–29119, 3rd edn. Working Group on Asynchronous Circuit Design (ACiD-WG).
  5. 5.
    Cortadella J, Kishinevsky M, Kondratyev A, Lavagno L, Yakovlev A (1997) Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. In: IEICE Trans Inf. and Syst, pp 315–325Google Scholar
  6. 6.
    Fuhrer RM, Nowick SM, Theobald M, Jha NK, Lin B, Plana L (1999) Minimalist: An Environment for the Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines. Technical Report CUCS-020–9. Columbia University, Computer Science DepartmentGoogle Scholar
  7. 7.
    Yun KY, Dill DL (1992) Automatic synthesis of 3D asynchronous state machines. In: ICCAD92, pp 576–580. Santa Clara, CA.Google Scholar
  8. 8.
    Martin AJ (1990) Programming in VLSI: from communicating processes to delay-insensitive circuits. In: Developments in Concurrency and Communication, pp 1–64. Hoare CAR, UT Year Programming SeriesGoogle Scholar
  9. 9.
    Edwards D, Bardsley A (2002) Balsa: an asynchronous hardware synthesis language. In: The Computer Journal, Volume 45, Issue 1, pp 12–18Google Scholar
  10. 10.
    Berkel KV (1993) Handshake circuits–an asynchronous architecture for VLSI programming. Cambridge University Press, CambridgezbMATHGoogle Scholar
  11. 11.
    Quartana J, Fesquet L, Renaudin M (2005) Modular asynchronous Network-on-Chip: application to GALS system rapid prototyping. In: Very Large Scale Integration Systems (VLSI-SoC’05). Perth, AustraliaGoogle Scholar
  12. 12.
    Koch-Hofer C, Renaudin M, Thonnart Y, Vivet P (2007) ASC, a SystemC extension for modeling asynchronous systems, and its application to an asynchronous NoC. In: 1st International Symposium on Networks-on-Chip (NoC’07). Princeton, NJGoogle Scholar
  13. 13.
    IEEE Std 1666–2005, SystemC Language Reference Manual (2005)Google Scholar
  14. 14.
    Hoare CAR (1978) Communicating Sequential Processes. In: Communications of the ACM, Volume 21, Issue 8, pp 666–677Google Scholar
  15. 15.
    Lamport L (1978) Time, clocks, and the ordering of events in a distributed system. In: Communications of the ACM, Volume 21, Issue 7, pp 558–565Google Scholar
  16. 16.
    Ashkinazy A, Edwards D, Fansworth C, Gendel G, Sikand S (1994) Tools for validating asynchronous digital circuits. In: 1th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC’94), pp 12–21. Salt Lake City, UTGoogle Scholar
  17. 17.
    Chakraborty S, Dill DL, Yun KY, Chang KY (1997) Timing analysis for extended burst-mode circuits. In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC’97), pp 101–111. Eindhoven, The NetherlandsGoogle Scholar
  18. 18.
    Karlsen PA, Røine PT (1999) A timing verifier and timing profiler for asynchronous circuits. In: 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC’99), pp 13–23. Barcelona, SpainGoogle Scholar
  19. 19.
    Viaud E, Pêcheux F, Greiner A (2006) An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles. In: Design, Automation and Test in Europe (DATE’06). Munich, GermanyGoogle Scholar
  20. 20.
    Martin AJ (1993) Synthesis of Asynchronous VLSI Circuits. Internal Report, Caltech-CS-TR-93–28. Caltech Institute of Technology, Pasadena, CAGoogle Scholar
  21. 21.
    Sutherland IE (1989) Micropipelines. In: Communication of the ACM, Volume 32, Issue 6, pp 720–738Google Scholar
  22. 22.
    Open SystemC Initiative (2007) SystemC v2.2.
  23. 23.
    Karim F, Nguyen A, Dey S, Rao R (2001) On-chip communication architecture for OC-768 network processors. In: Design Automation Conference (DAC’01). Las Vegas, NV, pp 678–683Google Scholar
  24. 24.
    IEEE Std 1364–2001, Behavioural languages–Part 4: Verilog hardware description language (2001) pp 349–374Google Scholar
  25. 25.
    Helmstetter C, Maraninchi F, Maillet-Contoz L, Moy M (2006) Automatic Generation of Schedulings for Improving the Test Coverage of System-on-a-Chip. Verimag Research Report, TR-2006–6Google Scholar
  26. 26.
    Renaudin M, Rigaud JB, Dinh Duc AV, Rezzag A, Sirianni A, Fragoso J (2002) TAST CAD Tools. TIMA Research Report. TIMA–RR-02/04/01—FRGoogle Scholar

Copyright information

© Springer Science + Business Media B.V 2008

Authors and Affiliations

  • Cédric Koch-Hofer
    • 1
  • Marc Renaudin
    • 1
  1. 1.TIMA laboratoryGrenobleFrance

Personalised recommendations