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Transactor-Based Formal Verification of Real-Time Embedded Systems

  • D. Karlsson
  • P. Eles
  • Z. Peng
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 10)

Abstract

With the increasing complexity of today’s embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some components are described at high levels of abstraction, whereas others are described at low levels. Components in single abstraction level designs communicate through channels, which capture essential features of the communication. If the connected components communicate at different abstraction levels, then these channels are replaced with transactors that translate requests back and forth between the abstraction levels. It is important that the transactor still preserves the external characteristics, e.g. timing, of the original channel. This chapter proposes a technique to generate such transactors. According to this technique, transactors are specified in a single formal language, which is capable of capturing timing aspects. The approach is especially targeted to formal verification.

Keywords

Transactor formal verification petri-net regular expressions embedded systems 

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References

  1. 1.
    Bombieri N, Fummi F, Pravadelli G (2006) On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL. Proc. ACM/IEEE Design and Test in Europe, Munich, Germany, 6–10 MarchGoogle Scholar
  2. 2.
    Akella J, McMillan K (1991) Synthesizing Converters between Finite State Protocols. Proc. International Conference on Computer Design, Cambridge, MA, Oct. 15–15, pp. 410–413Google Scholar
  3. 3.
    Passerone R, Rowson JA, Sangiovanni-Vincentelli, A (1998) Automatic Synthesis of Interfaces between Incompatible Protocols. Proc. Design Automation Conference, San Francisco, CA, June, pp. 8–13Google Scholar
  4. 4.
    Bombieri N, Fummi F, Pravadelli G (2006) A TLM Design for Verification Methodology. IEEE Ph.D. Research in Microelectronics and Electronics, Otranto (LE), Italy, 11–15 June, 337–340Google Scholar
  5. 5.
    Balarin F, Passerone R (2006) Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation. Proc. Design and Test in Europe, Munich, Germany, pp. 1013–1018Google Scholar
  6. 6.
    Asarin E, Caspi P, Maler O (1997) A Kleene Theorem for Timed Automata. Proc. Logic in Computer Science, Warsaw, Poland, June, pp. 160–171Google Scholar
  7. 7.
    Karlsson D, Eles P, Peng Z (2007) Formal Verification of Component-based Designs. Journal of Design Automation for Embedded Systems 11(1):49–90CrossRefGoogle Scholar
  8. 8.
    Alur R, Courcoubetis C, Dill DL (1990) Model Checking for Real-time Systems. Theoretical Computer Science 414–425Google Scholar
  9. 9.
    UPPAAL homepage: http://www.uppaal.com/
  10. 10.
    Cortés LA, Eles P, Peng Z (2000) Verification of Embedded Systems Using a Petri Net Based Representation. Proc. International Symposium on System Synthesis, Madrid, Spain, pp. 149–155Google Scholar
  11. 11.
    Alur R, Dill DL (1994) A Theory of Timed Automata. Theoretical Computer Science 126:183–235zbMATHCrossRefMathSciNetGoogle Scholar
  12. 12.
    Kozen DC (1997) Automata and Computability. Springer, New York.zbMATHGoogle Scholar

Copyright information

© Springer Science + Business Media B.V 2008

Authors and Affiliations

  • D. Karlsson
    • 1
  • P. Eles
    • 1
  • Z. Peng
    • 1
  1. 1.Department of Computer and Information ScienceLinköpings universitetLinköpingSweden

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