Asynchronous On-Line Monitoring of Logical and Temporal Assertions

  • K. Morin-Allory
  • L. Fesquet
  • B. Roustan
  • D. Borrione
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 10)


PSL is a standard formal language to specify logical and temporal properties under the form of assertions. This paper presents the synthesis of PSL assertions into asynchronous hardware monitors that can be linked to the circuit under monitoring. The checker synthesis is based on a systematic interconnection of asynchronous primitive monitors corresponding to PSL operators. The asynchronous monitors are implemented with quasi delay insensitive logic which gives reliable and robust monitors in the case of truly asynchronous events, temperature or voltage variations. These monitors are applicable to a wider range of verification tasks such as the communications among globally asynchronous modules or in safe or secure applications.


PSL SVA hardware monitors asynchronous circuits 


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Copyright information

© Springer Science + Business Media B.V 2008

Authors and Affiliations

  • K. Morin-Allory
    • 1
  • L. Fesquet
    • 1
  • B. Roustan
    • 2
  • D. Borrione
    • 1
  1. 1.TIMA LaboratoryGrenobleFrance
  2. 2.ENSERG/INPGGrenobleFrance

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