An Enhanced SystemC UML Profile for Modeling at Transaction-Level

  • S. Bocchio
  • E. Riccobene
  • A. Rosti
  • P. Scandurra
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 10)


This chapter describes a UML2 profile for the SystemC language, which takes into account the language improvements as specified in the IEEE 1666 SystemC Standard and effectively provided in the SystemC 2.2 simulator as foundation for Transaction-Level Modeling (TLM). The profile is a set of modeling constructs which lift both the structural and behavioral features of SystemC to UML level. It is part of a model-driven HW-SW co-design methodology based on the UML2, a SystemC UML profile for the HW side, and a multi-threaded C UML profile for the SW side, which allows modeling of the system at higher levels of abstraction (from a functional executable level to Register Transfer Level) and supports automatic code-generation/back-annotation from/to UML models.


Embedded systems system-level design SystemC UML UML profiles 


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Copyright information

© Springer Science + Business Media B.V 2008

Authors and Affiliations

  • S. Bocchio
    • 1
  • E. Riccobene
    • 2
  • A. Rosti
    • 1
  • P. Scandurra
    • 2
  1. 1.STMicroelectronics R&IAgrate BrianzaItaly
  2. 2.University of Milan – DTICremaItaly

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