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Mixed-Level Modeling Using Configurable MOS Transistor Models

  • Jürgen Weber
  • Andreas Lemke
  • Andreas Lehmler
  • Mario Anton
  • Sorin A. Huss
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 10)

Abstract

This contribution presents an approach to mixed-level modeling using configurable MOS transistor models as part of a behavioral model. All effects of the complete MOS transistor model can be specifically enabled or disabled in the configurable model. By activating only the effects required for the behavioral model, simulation times can be reduced significantly with very little effort. The new method is demonstrated by partitioning the MOS level-1 transistor model according to effects and implementing a configurable MOS level-1 transistor model in Verilog-A. Several examples of use will show the reduction in simulation time. The proposed approach can be used with any type of transistor model and is easily integrated in circuit simulators such as SPICE.

Keywords

mixed-level modeling Verilog-A behavioral model configurable MOS transistor virtual test 

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Copyright information

© Springer Science + Business Media B.V 2008

Authors and Affiliations

  • Jürgen Weber
    • 1
  • Andreas Lemke
    • 1
  • Andreas Lehmler
    • 1
  • Mario Anton
    • 1
  • Sorin A. Huss
    • 2
  1. 1.Atmel Germany GmbHHeilbronn
  2. 2.Integrated Circuits and Systems, Department of Computer ScienceTU DarmstadtGermany

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