The design of a single-bit 5th-order quadrature continuous-time IF-to-baseband ΣΔADC for AM/FM/IBOC car radios [1] is presented in this chapter. This ADC enables the realization of a quadrature low-IF receiver architecture with reduced number of external components described earlier in section 2.7.
Section 5.1 describes the quadrature IF-to-baseband conversion system together with the continuous-time ΣΔmodulator system-level design. The IF mixer design is the subject of section 5.2. Special attention is given to the issue of subsampling of the quantization noise. The design of the 1st integrator is presented in section 5.3, and the performance requirements for continuous-time and switched-capacitor integrators are discussed. Section 5.4 presents the most important design issues regarding the high-order integrators and resonators. The feedforward coefficients and the single-bit quantizer are described in section 5.5. Section 5.6 discusses the design of a single-bit switched-capacitor feedback DAC and the issue of jitter sensitivity in continuous-time ΣΔmodulators. This section also presents the design of a reference voltage generator for the SC feedback DAC. Experimental results from two fabricated IC prototypes are presented and analysed in section 5.7.
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(2008). IF-to-Baseband ΣΔ ADC for AM/FM/IBOC Receivers. In: High-Resolution If-To-Baseband ΣΔ Adc For Car Radios. Analog Circuits And Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8164-4_5
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