Partitioning

Given a gate-level circuit, the goal of circuit partitioning problem is to divide the circuit into Kroughly equal-sized partitions. The traditional objective is to minimize the number of nets connecting gates in multiple partitions, which is typically called the “cutsize” in the literature. Other objectives include critical path delay, total power consumption, etc. This chapter presents sample problems related to the following works:

• Kernighan and Lin algorithm [Kernighan and Lin, 1970]

• Fiduccia and Mattheyses algorithm [Fiduccia and Mattheyses, 1982]

• EIG algorithm [Hagen and Kahng, 1992]

• FBB algorithm [Yang and Wong, 1996]

The first two algorithms are so called move-based, where the given partitioning solution is improved by moving the gates across the partitions. The third algorithm minimizes so called the “ratio cut” metric based on eigenvector computation. The last algorithm adopts the maximum flow model to perform partitioning under cutsize minimization.