Abstract
This chapter contains an introduction to FPGA technology that includes architecture, power consumption and configuration models, as well as an extensive survey of existing fine-grain reconfigurable architectures that have emerged from both academia and industry. All aspects of the architectures, including logic block structure, interconnect, and configuration methods are discussed. Qualitative and quantitative comparisons in terms of testability, technology portability, design flow completeness and configuration type are shown. Additionally, the implementation techniques and CAD tools (synthesizers, LUT-mapping tools and placement and routing tools) that have been developed to facilitate the implementation of a system in reconfigurable hardware by the industry (both by FPGA manufacturers and third-party EDA tool vendors) and academia are described.
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References
Hsieh, H., W. Carter, J. Y. Ja, E. Cheung, S. Schreifels, C. Erickson, P. Freidin, and L. Tinkey, “Third-generation architecture boosts speed and density of field-programmable gate arrays”, in Proc. Custom Integrated Circuits Conf., 1990, pp. 31.2.1–31.2.7.
Ahrens, M., A. El Gamal, D. Galbraith, J. Greene, and S. Kaptanoglu, “An FPGA family optimized for high densities and reduced routing delay”, in Proc. Custom Integrated Circuits Conf., 1990, pp. 31.5.1–31.5.4.
George, V. and J. M. Rabaey, “Low-Energy FPGAs: Architecture and design”, Kluwer Academic Publishers, 2001.
http://www.actel.com, Accelerator Series FPGAs – ACT3 Family, Actel Corporation, 1997.
http://www.actel.com, SX Family of High Performance FPGAs, Actel Corporation, 2001.
Butts M. and Batcheller J, “Method of using electronically reconfigurable logic circuits”, 1991, US Patent 5,036,473.
Hauck S, “The roles of FPGAs in reprogrammable systems”, in Proc. IEEE ,v>86, 4, pp. 615–638, 1998.
Rose, J., R. J. Francis, D. Lewis, and P. Chow, “Architecture of field-programmable array: The effect of logic block functionality on area efficiency”, IEEE Journal of Solid State Circuits, Vol. 25, No. 5, October 1990, pp. 1217–1225.
Kouloheris, J. L. and A. El Gamal, “FPGA Performance versus cell granularity”, Proceedings of the IEEE custom integrated circuits conference, San Diego, California, 1991, pp. 6.2.1–6.2.4.
Singh, S., J. Rose, P. Chow, and D. Lewis, “The effect of logic block architecture on FPGA performance”, IEEE Journal of Solid-State Circuits, Vol. 27, no. 3, March 1992, pp. 281–287.
He, J. and J. Rose, “Advantages of heterogeneous logic block architecture for FPGAs”, Proceedings of the IEEE Custom integrated circuits conference, San Diego, California, 1993, pp. 7.4.1–7.4.5.
H. Hsieh, W. Carter, J. Y. Ja, E. Cheung, S. Schreifels, C. Erickson, P. Freidin, and L. Tinkey, “Third-generation architecture boosts speed and density of field-programmable gate arrays”, in Proc. Custom Integrated Circuits Conf., 1990, pp. 31.2.1–31.2.7.
Trimberger, S. “Effects of FPGA Architecture on FPGA Routing”, in Proceedings of the 32nd ACM/IEEE Design Automation Conference (DAC), San Francisco, California, USA, 1995, pp. 574–578.
http://aplawrence.com/Makwana/nonvolmem.html
Betz, V. and J. Rose, “Cluster-based logic blocks for FPGAs: Area-Efficiency vs. Input sharing and size”, IEEE Custom Integrated Circuits Conference, Santa Clara, California, 1997, pp. 551–554.
http://www.altera.com/products/devices/stratix_II/features/Stratix II 90 nm Silicon Power Optimization.htm
“Reconfigurability requirements for wireless LAN products”, Electronic document available at http://www.imec.be/adriatic/deliverables/ec-ist-adriatic_deliverable-D1–1.zip
Trimberger, S. D., Carberry, A. Johnson, and J. Wong, “A time-multiplexed FPGA”, IEEE Symposium on field-programmable custom computing machines, 1997, pp. 22–28.
Schmit, H., “Incremental reconfiguration for pipelined applications”, 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM ‘97), Napa Valley, CA, April 1997, 99 16–18.
Hauck, S., “Configuration prefetch for single context reconfigurable coprocessors”, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 1998.
Hauck, S., Z. Li, and E. Schewabe, “Configuration compression for the xilinx XC6200 FPGA”, IEEE Symposium on FPGAs for Custom Computing Machines, 1998.
Li, K., Z. Compton, J. Cooley, S. Knol, and S. Hauck, “Configuration relocation and defragmentation for run-time reconfigurable computing”, IEEE Trans., VLSI System, 2002.
Li, Z., K. Compton, and S. Hauck, “Configuration caching techniques for FPGA”, IEEE Symposium on FPGAs for Custom Computing Machines, 2000.
Hauser, J. R. and J. Wawrzynek, “Garp: A MIPS Processor with a reconfigurable coprocessor”, University of California, Berkeley.
Wittig, R. D. and P. Chow, “One chip: An FPGA Processor with reconfigurable logic”.
Hauck, S., T. W. Fry, M. M. Holser, and J. P. Kao, “The chimaera reconfigurable functional unit”, IEEE Symposium on field-programmable custom computing machines, pp. 87–96, 1997.
Ye, Z. A., A. Moshovos, S. Hauck, and P. Banerjee, “Chimaera: A high-performance architecture with a tightly-coupled reconfigurable function unit”.
Zhang, H., V. Prabhu, V. George, M. Wan, M. Benes, A. Abnous, and J. M. Rabaey, “A 1V Heterogeneous reconfigurable processor IC for baseband wireless applications”, ISCA 2000.
George, V., H. Zhang and J. Rabaey, “The design of a low energy FPGA”, in Proc. of Int. Symp. on Low Power Electronics and Design (ISLPED) 1999, pp. 18.–193
Tau, E., D. Chen, I. Eslick, J. Brown, and A. DeHon, “A first generation DPGA implementation”, FPD’95, Third canadian workshop of field-programmable devices, May 29-June 1, 1995, Montreal, Canada.
Ebeling, C., G. Borriello, S. A. Hauck, D. Song, and E.A. Walkup, “TRIPTYCH: A new FPGA architecture”, in FPGA’s, W. Moore and W. Luk, Eds. Abingdon, U.K.L Abingdon, 1991, ch 3.1, pp. 75–90.
Borriello, G., C. Ebeling, S. A. Hauck, and S. Burns, “The triptych FPGA architecture”, IEEE Trans. VLSI Syst., Vol 3, pp. 491–500, Dec. 1995.
Hauck, S., G. Borriello, S. Burns, and C. Ebeling, “MONTAGE: An FPGA for synchronous and asynchronous circuits”, in Proc. 2nd Int. Workshop Field-Programmable Logic Applicat., Vienna, Austria, Sept. 1992.
Chow, P., S. O. Seo, D. Au, T. Choy, B. Fallah, D. Lewis, C. Li, and J. Rose, “A 1.2 μm CMOS FPGA using cascaded logic blocks and segmented routing”, in FPGA’s W. Moore and W. Luk, Eds. Abingdon, U.K.: Abingdon, 1991, ch 3.2, pp. 91–102.
George, V. and J. M. Rabaey, “Low-Energy FPGAs: Architecture and design”, Kluwer Academic Publishers, 2001.
Chiricescu, S., M. Leeser, and M. M. Vai, “Design and analysis of a dynamically reconfigurable three-dimensional FPGA”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 1, February 2001.
Chow, P., S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, and I. Rahardja, “The design of a SRAM-Based field-programmable gate Array-Part I: Architecture”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7, No. 2, June 1999.
Chow, P., S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, and I. Rahardja, “The design of a SRAM-Based field-programmable gate Array-Part II: Circuit design and layout”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7, No. 3, September 1999.
http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/index.htm
http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/index.htm
http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3_fpgas/index.htm
http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3l_fpgas/ index.htm
http://www.altera.com/products/devices/stratix2/st2-index.jsp
http://www.altera.com/products/devices/cyclone2/cy2-index.jsp
http://www.altera.com/products/devices/cyclone/cyc-index.jsp
http://www.altera.com/literature/ds/ds_stx.pdf
http://www.actel.com/products/fusion/
http://www.actel.com/products/pa3/index.aspx
http://www.actel.com/products/proasicplus/index.html
http://www.actel.com/docs/datasheets/AXDS.pdf
http://www.actel.com/varicore/support/docs/VariCoreEPGADS.pdf
http://www.actel.com/docs/datasheets/MXDS.pdf
http://www.atmel.com/atmel/acrobat/doc0264.pdf
http://www.quicklogic.com/
http://www.quicklogic.com/
http://www.lattice.com/
http://www.lattice.com/
http://ballade.cs.ucla.edu/∼trio/
http://ballade.cs.ucla.edu/software_release/rasp/htdocs/
http://ballade.cs.ucla.edu/software_release/ipem/htdocs/
Cha, Y-J., C. S. Rim, and K. Nakajima, “A simple and effective greedy multilayer router for MCMS”, Proceedings of the International Symposium on Physical Design, Napa Valley, California, United States, 1997.
http://cadlab.cs.ucla.edu/∼xfpga/fpgaEva/index.html
http://www.eecg.toronto.edu/∼jayar/software/psac/psac.html
http://www.eecg.toronto.edu/∼jayar/software/edif2blif/edif2blif.html
Electronic document available at http://www.eecg.toronto.edu/∼lemieux/sega/sega.html
Electronic document available at ftp://ftp.eecg.toronto.edu/pub/software/pgaroute/
http://www.eecg.toronto.edu/EECG/RESEARCH/tmcc/tmcc/
Electronic document available at ftp://ftp.eecg.toronto.edu/pub/software/Chortle/
Electronic document available at http://www.eecg.toronto.edu/∼vaughn/vpr/vpr.html
Kara K., W. Poon, A. Yan, and S. J. E. Wilton, “A flexible power model for FPGAs”, 12th International Conference, FPL 2002 Montpellier, France, September 2002.
http://www.actel.com/download/software/libero
http://www.actel.com/products/software/designer
http://www.embeddedstar.com/weblog/2006/08/22/actel-silicon-sculptor-3-fpga-tool/
http://www.actel.com/documents
http://www.actel.com/documents/SiExIIpib.pdf
http://www.cadence.com/company/newsroom/press_releases/pr.aspx?xml=013101_SPW
www.cadence.com/whitepapers/FPGA_Dev_Using_NC-Sim.pdf.
http://www.orcad.com
http://www.cadence.com/datasheets/4492C_IncisiveVerilog_DSfnl.pdf
http://www.mentor.com/products/fpga_pld/fpga_advantage/index.cfm
http://www.mentor.com/products/fpga_pld/hdl_design/hdl_designer_series/
http://www.embeddedstar.com/software/content/m/embedded239.html
http://www.mentor.com/products/fpga_pld/hdl_design/hdl_detective/
http://www.mentor.com/products/fpga_pld/hdl_design/hdl_author/
http://www.mentor.com/products/fpga_pld/news/hds2002_1_pr.cfm
http://www.mentor.com/products/fpga_pld/synthesis/
http://www.mentor.com/products/fpga_pld/synthesis/leonardo_spectrum/
http://www.model.com
http://www.quicklogic.com
http://www.embeddedstar.com/software/content/s/embedded382.html
http://www.fpgajournal.com/news_2006/04/20060411_01.htm
http://www.synplicity.com/products/synplifypremier/index.html
http://www.synplicity.com/literature/pdf/hdl_analyst_1103.pdf
http://www.synplicity.com/corporate/pressreleases/2003/SYB-207final.html
http://www.fpgajournal.com/news_2007/01/20070129_06.htm
http://www.synopsis.com
http://www.altera.com/products/software/products/quartus2/qts-index.html
http://www.xilinx.com
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Tatas, K., Siozios, K., Soudris, D. (2007). A Survey of Existing Fine-Grain Reconfigurable Architectures and CAD tools. In: Vassiliadis, S., Soudris, D. (eds) Fine- and Coarse-Grain Reconfigurable Computing. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6505-7_1
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DOI: https://doi.org/10.1007/978-1-4020-6505-7_1
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